This research paper introduces a low-power Physically Unclonable Function (PUF) design utilizing well-calibrated 14 nm FinFET technology. By leveraging the inherent process variations encountered during FinFET fabrication, the design exploits the uniqueness of each device. The implementation involves using a lookup table-based approach in the Cadence Virtuoso environment to create FinFET based inverters. To describe the low power consumption of FinFET technology, first, this research focuses on constructing a 3-stage Ring Oscillator (RO) with a power dissipation of 64.2 $\mu \mathrm{W}$ . Additionally, a significant contribution of this work is the development of a 32-bit PUF circuit, which utilizes 64 of these ROs. This novel design takes advantage of the quasi-planar structure and increased process variability offered by the 14 nm FinFET technology. The integration of these components enables efficient power utilization while maintaining the desired PUF functionality. To assess the uniqueness of the responses generated by 120 different PUFs, Monte Carlo simulations are conducted on 7680 points. The hamming distance between the generated response pairs is employed to quantify the uniqueness, resulting in an observed value of 50.05%. Additionally, an entropy evaluation is performed, yielding a calculated entropy of 0.987. Furthermore, a comparative analysis provides valuable insights by comparing the work presented with prior research contributions.

For future Analog and RF SoCs (System on Chip) design, 14 nm SOI FinFET is the potential candidate due to its better SCE (Short Channel Effect) capability and higher current drive strength. The Channel region of FinFET is confined by low thermal conductivity HiK material which offers a weaker heat flow path than classical MOSFET. It causes the self-heating effect, which leads to higher lattice temperature. Beyond the negative Differential Conductance (NDC) point, ON current starts decreasing due to high lattice temperature. The NDC point is a critical design parameter for Analog and RF circuit applications since the output conductance is negative beyond this point. Lattice temperature is highly dependent on the Surface to Volume ratio of FinFET, and the NDC point is the function of lattice temperature. So, in this work, Electrothermal simulation was performed on experimentally calibrated 14 nm SOI FinFET using Synopsys TCAD. Variation of lattice temperature with aspect ratio at a different gate length, extension length and fin height is studied. We have analyzed and optimized the NDC point in 14 nm SOI FinFET using the Surface to Volume Ratio approach and provided the design guidelines for Analog and RF circuit design.

Stacked nanosheet field effect transistors are the potential candidate for future CMOS-based design as a successor of the FinFET technology due to their improved short channel effect and higher effective width in the same area footprint. This research investigates the impact of self-heating and substrate effects on the small signal conductance and capacitance of FinFET and nanosheet devices using Synopsys TCAD. The presence of substrate introduces transitions in the conductance–frequency plot due to the substrate and self-heating effects in FinFET examined. Further, nanosheet devices show similar trends, with less pronounced substrate effects which is discussed first time in this work. Analyzing the effect of the type of substrate, voltage, work function, substrate doping, and electrode resistance variation provides further insights into the substrate-induced transition in the Nanosheet FET. These findings contribute to advancing nanoscale device technologies, particularly in RF applications.

Non-quasi-static small-signal models are essential for exploring the high-frequency (HF) behavior of the FinFET. In this paper, we propose a modified small-signal model for a multi-fin (MF) FinFET to extract the intrinsic and extrinsic parameters using Y-parameters extracted from TCAD. The gate resistance plays a significant role in optimizing the HF behavior with the varying numbers of fins in the MF configuration. We also test the model’s accuracy with increasing temperature up to 425 K. Using well-calibrated TCAD models, we further analyze the analog and linearity figures of merit, including cutoff frequency ( f _T ), the maximum frequency of oscillation ( f _max ), transconductance (g _m ) and higher-order derivatives such as g _m2 , g _m3 , VIP _2 , and VIP _3 . Thus, the behavior of intrinsic and extrinsic parasitic resistance and capacitance is worth exploring to determine the device operation in the frequency range of >100 GHz.

This paper focuses on investigating the impact of NBTI degradation on p-FinFETs, a major reliability concern. The impact of donor type interface traps on single and multifin FinFET structures are considered for both device and circuit aspects. The degradation of device performance occurs due change in threshold voltage (Vth) and drain current caused by traps. This study extends to analyze the effect of traps on the Voltage Transfer Characteristic (VTC) and transient behavior in an inverter, followed by a study of the Ring Oscillator (RO). We precisely evaluate parameter changes and differentiate the impact among 1-Fin, 2-Fin, and 3-Fin structures. Under NBTI, device reliability concern, the End of Lifetime (EOL) is achieved at a threshold voltage shift of 50 mV, occurring at a trap concentration of 1.25x10(12) cm(-2). While the change in Vth is consistent across single and multi-fin FinFETs parameters however Subthreshold Slope (SS), transconductance (gm) and DIBL (Drain Induced Barrier Lowering) exhibit more significant variations and degradation, particularly in 2-Fin and 3-Fin structures. In terms of Ring Oscillator (RO) performance, the impact is less pronounced in 1-Fin structures, resulting in finer performance compared to 2Fin and 3-Fin structures.

The interconnected power systems (IPS) are vulnerable because of sudden perturbations in the load, system parameters, and environmental variations, etc. In this IPS design, load frequency control (LFC) plays a very important role. It is observed that the conventional IMC design cannot be the best option in the case of the LFC problem of IPS in the presence of uncertain time delay or uncertain communication delay. In view of this, this paper focused on multi-modal-based internal model control (IMC) scheme for the design of a robust IMC controller for better closed-loop performance as well as disturbance rejection. This approach is based on the Multi-modal concept of T. Mustapha et al. In order to show the superiority of the proposed approach, the comparison has been done using well-known established IMC-based approaches on load frequency control, such as Saxena & Hote’s method, and W. Tan’s method. The performance measures such as integral error (IE), integral square error (ISE), integral absolute error (IAE), and integral time absolute error (ITAE) indicate the superiority of the proposed approach.

This study investigates the influence of heavy ion irradiation on thin film transistors (TFTs) based on an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. Through the use of Technology Computer-Aided Design (TCAD) simulations, we analyze the impact on device performance. We examine the ambipolar device characteristics by varying the thickness of the active layer (Poly-Si) and studying the corresponding physics. Our results reveal that reducing the active layer thickness from 140 to 80 nm decreases the magnitude of the threshold voltage (|VT|) for both nMOS and pMOS operating voltages. Additionally, the subthreshold slope is reduced for both nMOS and pMOS as the active layer thickness is decreased from 140 to 80 nm.Further, we investigated the transient response of the drain current to heavy ion irradiation in the sensitive regions across the Schottky barrier-based source and drain. We specifically analyze the phenomenon of bipolar amplification for various Linear Energy Transfer (LET) values, ranging from 0.1 MeV cm2/mg to 100 MeV cm2/mg. Our findings indicate that increasing the LET values from 0.1 MeV cm2/mg to 100 MeV cm2/mg results in amplified bipolar behavior and a drain current overshoot of over 10 % for both pMOS and nMOS operating voltages. To summarize, this work highlights the effects of heavy ion irradiation on TFTs with an a-Si:H/PolySi active layer and Schottky barrier-based source and drain. The study explores the influence of active layer thickness on device characteristics and demonstrates the transient response of drain current under different LET values. These findings contribute to a better understanding of the behavior and performance of TFTs subjected to heavy ion irradiation.

In this work, we present a novel investigation of the Random Telegraphic Noise (RTN) signal in nickel-silicon contacts with and without the interfacial oxide layer, marking the first instance of such an analysis. The observed multilevel RTN signal has revealed the existence of two distinct traps in both scenarios. Specifically, our analysis has unveiled that in the case of an interfacial oxide layer, one of the traps is located near the interface, resulting in barrier height fluctuations of up to 11.5 %. Meanwhile, the other trap situated away from the interface, yields barrier height fluctuations of up to 7.3 %. In situations where the interfacial layer is absent, we report barrier height fluctuations of up to 9.2 % attributed to the first trap and up to 6.0 % due to the second trap, shedding light on the critical influence of the interfacial oxide layer on these fluctuations.

This work comprehensively focuses on the intricate thermal dynamics of 5nm Gate-All-Around Stacked Nanosheet Field-Effect Transistors (GAA-SNFETs), revealing the significant influence of thermal cross-talk (TCT) and parameter dependencies. A well-experimentally calibrated Synopsis 3D TCAD structure is used to reveal that TCT influences temperature distribution across sheets, with the central sheet experiencing elevated heating due to pronounced TCT. Furthermore, our exploration of lattice temperature’s response to device parameters and operational conditions, including width variation and operating voltage, unveils intricate non-linear relationships. In the face of the inherent complexity in analytically modeling these phenomena, we employ an ML-RFR model. Our model achieves both precision and efficiency in predicting the lattice temperature of different sheets, which can consider TCT. We demonstrate a close alignment between predicted and actual temperatures across different sheets through a proposed model. In essence, our study provides a Machine learning-based approach to study and model the thermal cross-talk in GAA-SNFET, highlighting the potential of machine learning for optimizing nanoscale device design and operation.

The interconnected power system has evolved rapidly in the modern era. This results in a new global infrastructure for distributed systems from locally distributed systems. This established a network-based cyber-physical system (NCPS). Many crucial operations need to be performed for a better quality of power. Among them, frequency stabilisation is a significant concern against uncertainties, random load changes, etc. The fluctuations in frequency can cause a severe issue for the whole power system, so load frequency control (LFC) is an important task to be performed. Due to NCPS, LFC functioning is highly vulnerable to cyber threats. Different kind of attacks can affect LFC operations, such as denial of service (DoS), false data injection (FDI), time delay attacks (Tda), etc. The above problems motivate us to study and analyse the cyber threat issues in NCPS during LFC operations. In view of the above, various existing cyber-attacks were discussed. Further, various detection approaches using machine learning (ML) were studied. In order to show the application of the ML-based control technique, a new PID tuning approach is proposed, which is based on the gradient descent algorithm (GDA) for the mitigation of cyber-attacks, especially for the single area power system model.

In this article, we have studied the effects of gamma and heavy ion radiation on 5nm stacked nanosheet FET and Fork-sheet FET and analyzed the impact of radiation on circuitlevel characteristics. These analyses are carried out by using Three-Dimensional Technology Computer-Aided Design (3-D TCAD) simulations. By exposing gamma rays and heavy ion, the performance in terms of charge generation rate of nanosheet FET and Fork-sheet are investigated. Gamma particle and heavy-ion impacts are studied at the device and circuit levels. The results of Fork-sheet FET are compared with the results of gate-all-around nanosheet FET. After comparison, we found that radiation has a stronger influence on Fork-sheet than Nanosheet.

Atomic layer deposition (ALD) of tungsten-disulfide (WS2) on silicon-dioxide (SiO2) substrate had been modelled using a kinetic Monte Carlo (KMC) method which considered kinetic extrapolation of reaction entropy and enthalpy between the two proposed reaction limits that define possible initial and final phases of the WS2 ALD reaction, and stochastic adsorption or desorption of molecules was calculated based on that. The KMC as developed here can remarkably model growth delay as a function of deposition temperature, which was also observed at the time of actual ALD of WS2 on SiO2 substrate. The model was calibrated with the available experimental data, which employed a simplified computational algorithm that treated precursors in the gas phase as plain molecules, which bore no specific chemical identities those however could kinetically adsorb/desorb on/from the available substrate sites based on stochastic rates at a given instant of WS2 ALD cycle. KMC was able to resolve lateral versus vertical growth of WS2 as occurs versus time, and calibration of modelled areal density of WS2 atoms those evolved with ALD cycles agreed well with the experiment. KMC model as demonstrated here can be employed for faster optimization of WS2 - monolayers on SiO2 substrate against ALD temperature as a crucial process parameter.

Owing to its improved short channel effect and higher drive current compared to existing 14 nm FinFET, 5 nm Stacked Nanosheet Field Effect Transistor (SNFET) is projected as the future technology node for Integrated circuit (ICs) design beyond 7 nm. It is widely known that the physics of thermal transport and management in SNFETs is quite complicated due to its confined oxide geometry around the channel. To investigate and analyze the thermal hot spot creation inside SNFET channel due to Self-Heating Effect, multiscale electro-thermal modeling of experimentally calibrated SNFET is provided. The hotspot inside the channel region results in mobility degradation and consequently current deterioration. This work offers guidelines for optimizing hotspot position and size with the help of device parameter variation using industry-standard Synopsys© QuantumATK tool and TCAD tool. A key component of hotspot optimization in SNFETs is interface thermal resistance (ITR). By using Non-Equilibrium Green Function (NEGF) theory, thermal transport in SNFET studied and ITR of various interfaces in the presence of stress and defects was computed, and its impact on hotspot variation was explored. It was found that the variation of the ITR is consistent with Non-Equilibrium Molecular Dynamics (NEMD) too.

Cooperative game theory (CGT) was applied for fin pitch design in a multifin (MF)-FinFET, and the approach was found fruitful to reduce the self-heating effect (SHE) considerably. Individual fin contribution in MF-FinFET was numerically estimated within the framework of CGT using postprocessed results obtained from a calibrated special technology computer aided design (TCAD) simulation paradigm which was engaged to determine SHE due to various fin combinations in a 14-nm five fin reference silicon-on-insulator (SOI)-FinFET. Fin contributions to SHE were further employed for fin pitch optimization for better thermal management. Furthermore, area constraint had been accounted in the same optimization rule. The scheme was found weakly sensitive to allowable process variation (lithography pitch); however, it strictly remained SHE bias and device contact geometry independent. Electrical characteristics of reference MF-FinFET were found to be well preserved even under this fin pitch optimization

Stacked Nanosheet Transistor (SNST) is the potential candidate for the Digital, Analog, and RF application due to its better SCE, ON current and area footprint. This work performs 3D FEM calculation of SNST to RF properties analysis for Single Gate Contact (SGC) and Double Gate Contact (DGC). Effect of SGC & DGC analyzed on gate resistance (Rg) and capacitance (C gg ) of the device, which limits the unity gain frequency (f T ) and maximum frequency of oscillation (f MAX ). Variation of Rg with the device parameters such as gate length, sheet width, thickness, sheet pitch, stack spacing, and number of sheets are analyzed. Effect of SGC and DGC on R g , C g , f T and f MAX explained. The Optimum number of sheets required for better RF FOM is calculated.

The main aim of attackers targeting Cyber- Physical Systems (CPS) is to compromise the control and monitoring applications facilitated by the cyber layer. The Gain (also called covert or DoS) attack and the Man-in-the-Middle(MitM) (also called false data injection) attack can disrupt the operation of control systems. In this paper, we have introduced Internal Model Control (IMC) as one of the resilient control techniques for detecting and mitigating cyber-attacks. Here, we considered a DC-DC PWM buck converter designed based on the state space averaging(SSA) technique as a plant model. Further, we developed an IMC-PID conventional controller for this model with introduced cyber-attacks in the communication network. The final IMC controller is expressed in the discrete domain as a series combination of Proportional, Integral, and Derivative (PID) terms. The simulations are conducted in MATLAB/SIMULINK environment and validated on a hardware setup using the WAVECT Controller.

This work presents a machine learning regression-based surrogate model of Single Event Upset (SEU) transient current for circuit-level simulation. The phenomenal success of FinFET technology in terms of integration and performance over planar MOSFETs has paved the way for their usage in aerospace-integrated circuits and defense applications. However, their sensitivity to radiation hazards in such applications remains the primary concern. With the recent technological advancement, the semiconductor industry has shifted its focus to device analysis before fabrication so that the circuit designers may mitigate radiation effects before actual fabrication. The Technology Computer-Aided Design (TCAD) tools are being used to design the structure and analyze the device parameters. However, these tools are computationally intensive and time-consuming. This work explores the feasibility of using machine learning for predicting device parameters and Single Event Transient (SET) current using an unsupervised learning technique. A 14nm 3D FinFET device is designed using the TCAD tool, and a dataset with various parameters is generated. This dataset is used to train (1) a Random Forest Regressor model and (2) A feedforward neural network for predicting SET pulse current. The 10% dataset was randomly chosen as a subset to test this algorithm and predict SET current. The comparison between actual and predicted data shows high accuracy. For example, the random forest algorithm achieves a mean square error of 1.49e-3 for the test dataset. This shows that machine learning models can replace TCAD for accelerating device performance analysis for large-scale circuits. The conventional TCAD simulation takes 4 hours per simulation on a Xeon W1350P processor and 32 GB RAM hardware. By contrast, our proposed model takes only 8–10 seconds to predict the SET current. This study can help designers mitigate SET effects in the design phase. The source-code of our proposed machine-learning models is available at https://github.com/vihhu53/MLSEUFinfet.

Beyond 7 nm technology nodes, a Stacked Nanosheet Field Effect Transistor (SNT) is a potential candidate to continue device scaling due to its higher ON/OFF current ratio and less Short Channel Effect than FinFET. However, its gate all-around structure with low thermal conductive HiK oxide material exacerbates the Self-Heating Effect (SHE) issue in the SNT. Further, a dielectric inserted beneath SNT to reduce leakage current disrupts the primary heat flow path through the substrate, aggravating the Self Heating Effect (SHE). This study focuses on exploring the thermal aspect of the SNT with partial and complete dielectric insertion under the device from a performance and reliability perspective. A 3D electrothermal analysis has been performed using Synopsys TCAD tool. The effect of partial and complete dielectric insertion under the device on lattice temperature was investigated in the case of single and double-stack nanosheet transistors. The effects of dielectric insertion on channel and substrate temperature were analyzed. Its variation with width, extension length, interface thermal resistance, and the number of sheets and stack pitch of SNT are discussed. Sheet-dependent heat flow through the substrate and source/drain contact explained for different types of SNT structures and its effect on device performance and reliability discussed. To discuss the effect of multiple parameters variation on the lattice temperature of the device, Analysis of Variance (ANOVA) method was used. It was found that complete dielectric insertion leads to a severe heating issue in the SNT compared to partial and without dielectric insertion.

The Proportional-Integral-Derivative (PID) controller tuned by Internal-Model-Control (IMC) is extensively used in industrial control applications. This methodology offers an excellent trade-off between the setpoint tracking and disturbance rejections, and also provides better robustness. In this paper, we suggest a simple and straightforward approach for designing IMC based PID controller with a fractional filter for electrical engineering applications. Due to the use of a fractional order filter, the flexibility of tuning the parameters is increased. To verify the suggested method's utility, simulation analysis has been done for the mathematical model of a rotational DC servo system (QUBETM-Servo 2) and single area power system (SAPS). The approach for controller design depicts proper set-point tracking and better disturbance rejections. The performance analysis of the controller which has been designed for the applications has been done based on the integral of error $(IE_{E})$ , integral square error $(ISE_{E})$ , integral absolute error $(IAE_{E})$ , and control efforts (CE). Finally, the robustness analysis has been done for a +50% change in the gain of the process.

In this era, with a great extent of automation and connection, modern production processes are highly prone to cyber-attacks. The sensor-controller chain becomes an obvious target for attacks because sensors are commonly used to regulate production facilities. In this research, we introduce a new control configuration for the system, which is sensitive to time delay attacks (TDA), in which data transfer from the sensor to the controller is intentionally delayed. The attackers want to disrupt and damage the system by forcing controllers to use obsolete data about the system status. In order to improve the accuracy of delay identification and prediction, as well as erroneous limit and estimation for control, a new control structure is developed by an Internal Model Control (IMC) based Proportional-Integral-Derivative (PID) scheme with a fractional filter. An additional concept is included to mitigate the effect of time delay attack, i.e., the smith predictor. Simulation studies of the established control framework have been implemented with two numerical examples. The performance assessment of the proposed method has been done based on integral square error (ISE), integral absolute error (IAE) and total variation (TV).