Microfluidic fully programmable valve array (FPVA) biochips emerge as programmable flow-based labs-on-a-chip consisting of a two-dimensional array of reaction chambers surrounded by four microvalves. Given a mixing tree (represents a sequence of mixing steps) for the target ratio, existing design automation algorithms (DAA) for sample preparation (mixing of reagents in a desired ratio through a sequence of mixing) on FPVA first find the suitable transport-free placement (avoids cumbersome transportation of fluid segment(s) between chambers) and scheduling of mixing operations. After that, reagents are loaded into designated mixer chambers by pushing fluids through input-to-output paths. Since the existing DAA for sample preparation did not consider fluid loading while finding the placement of mixing operations, it often requires a longer and more complex fluid loading path, increasing the sample preparation time and cost. In this paper, we leverage the combinatorial properties of the mixing tree to transform it in favor of finding simpler and shorter paths to load fluids. The simulation results reveal a considerable speedup in the fluid loading time and savings in reagent usage when the proposed algorithm is applied to the mixing tree.

Scheduling of mixing graphs is the first step of the design automation for the implementation of mixing graphs on microfluidic biochips. Depending on the biochip platform, the scheduling constraints may vary. For instance, if we consider a flow-based microfluidic biochip, then we have to consider the retention time while scheduling any mixing graph. The retention time of a flow-based microfluidic biochip is defined as the duration for which a latch valve can hold the pressure for a given pressure pulse and act as a normal valve. Violating retention time constraint can produce erroneous results for on-chip bioprotocol execution. Recently one method called time aware list scheduling (TALS) is reported in literature, which considers the retention time constraint while scheduling the mixing graphs without minimizing the scheduling length. However, the quality of a scheduling algorithm depends on the trade-off between the resource required and the scheduling length. In this work, we consider the retention time of latches as the scheduling constraint and proposed a novel heuristic-based approach called retention time aware scheduling (RTAS) that aims to minimize the scheduling length with slight increase in number of resources (on-chip mixers) required. Simulation results confirm that RTAS always outperforms the baseline ALAP and TALS in case of resources required and the scheduling length, respectively.

Post-disaster needs assessment plays a critical role in developing emergency response programs and disaster preparedness. An assessment of needs identifies possible interventions or assistance and the necessary resources for emergency responses. This emergency need assessment assists stakeholders in defining possible response options, evaluating the priorities of needs of affected communities, and determining what support will be required immediately. The prevalent use of social media in Indonesia highlights its significance as a crucial means of acquiring prompt, effortless, individualized, and geo-specific information regarding the demands and requirements of communities impacted by a calamity. This study aims to analyze the tweets posted by local communities affected by the 2018 Central Sulawesi earthquakes, tsunami, and liquefaction using the Social Network Analysis (SNA) method based on machine learning and natural language processing. Through this analysis, we intend to observe the spatial interaction and relationship among the affected areas of communities for the needs and concerns after the disaster to enhance the relief operation. We found that social media users, government, and humanitarian organizations effectively shared information during the disaster. This study also underlined that the behavioral responses of individuals to disasters were not limited to the disaster-stricken areas but extended far beyond them. This action suggests that they were willing to exhibit a more empathetic, benevolent, and philanthropic demeanor in the face of such traumatic events.

Micro-electrode-dot-array (MEDA) based digital microfluidic biochips have been developed for automated execution of bioprotocols, which are used in point-of-care diagnostics. In literature, many sample preparation algorithms are reported for determining the protocol graph (called as dilution tree) for automated dilution and mixing of two or more input fluids, which are pure and having infinite supplies. For dilution of a fluid from its related arbitrary stock solutions (RASS), out of existing methods GDA (Roy et al., JETC, 2014) uses only (1: 1) mixing model, and hRASS (Ghosh et al., ISDCS, 2022) uses various mixing models of maximum mixer-M (M is a positive integer) and every mixer is of the same size at each mixing node. A drawback of hRASS is to always use only one droplet of intermediate fluids to determine the dilution tree. In this paper, we propose a satisfiability modulo theory (SMT) based optimization technique to determine the dilution tree for a RASS problem instance having two criteria, where (a) the input fluids are expensive and overall cost is to be minimized (named as cRASS), and (b) the volume-wise availability of the input solutions are restricted (named as vRASS). Simulation results validate that using MEDA biochips with various mixer size constraints (M), cRASS can overcome the drawback of hRASS by reusing more than one droplet of intermediate fluids and determine the cost-effective dilution tree, whereas vRASS can determine the dilution tree for some of the problem instances when hRASS and cRASS cannot provide any solution under availability restrictions.

promising new generation microfluidic biochips consisting of a sea-of-micro-electrodes with dedicated detection circuit for each microelectrode. Moreover, the ability to manipulate discrete droplets of different volumes and to route them in any direction presents MEDA biochips as an advanced microfluidic technology. Due to similarity in the working principles, the reliability issues of both MEDA biochips and digital microfluidic biochips are similar. In this paper, we propose a module placement technique for MEDA biochips to improve the reliability of biochips. Reinforcement learning based placement method (RLPM) is designed for obtaining the reliability-aware placement of rectilinear shaped microfluidic modules. RLPM aims to minimize the area of a biochip while increasing its reliability. Simulation results confirm that on average RLPM minimizes the chip utilization area by 28.6% while enhancing the reliability of MEDA biochips compared to the state-of-the-art method.

Microfluidic biochips are being widely used for automating biochemical laboratory protocols, and several algorithms for automated sample preparation (dilution and mixing of reagent fluids) were reported in the literature. Almost all the sample preparation algorithms assumed the availability of pure sample fluid (i.e., with 100% concentration) ignoring the fact that pure samples may not always be readily available in stock. In fact, in many practical situations, a number of arbitrary concentrations of the sample fluid are discarded as wastes, which can be recycled to reduce the sample preparation cost (usage of pure sample, etc.) and generate the desired target concentration of the fluid required elsewhere. The traditional microfluidic biochips support (1:1) mixing model, for which there exists only a few old algorithms in literature, (namely generalized dilution algorithm, i.e., GDA and dilution/mixing with reduced wastage, i.e., DMRW) which were solely proposed for solving dilution problem by recycling arbitrary stock solutions (RASS) with traditional biochips. Although, a variety of microfluidic biochips have been developed over the years, no sample preparation algorithm is proposed for solving RASS problem for such modern biochips—which may provide a cost-effective solution for RASS. In order to fill this gap, in this paper, we propose a "cost-effective" heuristic solution (called hRASS) for dilution of a sample fluid from its arbitrary stock solutions catering various mixing models supported by modern microfluidic biochips. Simulation results confirm the superiority of the proposed method and show that hRASS can improve the solution quality by 36.8% and 21% on average for a large number of random testcases over state-of-the-art methods (e.g., DMRW and GDA, respectively).

Sample preparation is an inherent procedure of many biochemical applications, and digital microfluidic biochips (DMBs) proved to be very effective in performing such a procedure. In a single mixing step, conventional DMBs can mix two droplets in 1:1 ratio only. Due to this limitation, DMBs suffer from heavy fluid wastage and large number of mixing steps. However, the next generation DMBs, i.e., micro-electrode-dotarray (MEDA) biochips can realize multiple mixing ratios and are able to overcome a lot of those limitations. In this paper, we present a heuristic-based sample preparation algorithm, specifically a mixing algorithm called Division by Factor Method for Mixing that exploits the mixing models of MEDA biochips. We propose another mixing algorithm for MEDA biochips called Single Target Waste Minimization (STWM), which minimizes the wastage of fluids and determines an optimized mixing graph. Simulation results confirm that the proposed STWM method outperforms the state-of-the-art method in terms of minimizing the number of waste fluids, reducing the total reagent usage, and minimizing the number of mixing operations.

Silicon photonics (Si-photonics) has been established as a potential technology that integrates both electronic and optical circuits on single integrated circuits (ICs) in order to satisfy the increasing demand for high speed and low power in the emerging market of ICs. It has opened up the research directions in the domain of design automation for photonic ICs. On the physical layout of the optical circuits, it is a challenging task to obtain the optimal routing of optical waveguides, while minimizing all the parameters like the number of tracks, total bend loss, worst signal loss, total propagation loss and total crossing loss. In this paper, we proposed two non-Manhattan grid-based methods for reducing the bend loss, worst signal loss and tracks in optical channel routing. First, a 0–1 integer linear programming-based algorithm called minimizing bend loss (MBL) is proposed, which minimizes the total bend loss (TBL) and the worst signal loss (WSL) while reducing the number of tracks (T) over the state-of-the-art technique. The execution time of MBL is very high for the large input. Hence next, a scalable heuristic called reducing bend loss (RBL) is presented that provides a better balance between the reduction of the TBL and T over the state-of-the-art and MBL algorithms. Simulation results show that MBL can reduce the TBL and the WSL by an average of 57.9% and 63.1%, respectively, with an average increase of 12% in T over state-of-the-art algorithms. The simulation results show that the RBL reduces the TBL and the WSL by an average of 39.7% and 41.3%, respectively, with an average increase of 23.7% in T over state-of-the-art algorithms.

We present the design of a new large scale orchestration layer for accelerators. Our system, Pathways, is explicitly designed to enable exploration of new systems and ML research ideas, while retaining state of the art performance for current models. Pathways uses a sharded dataflow graph of asynchronous operators that consume and produce futures, and efficiently gang-schedules heterogeneous parallel computations on thousands of accelerators while coordinating data transfers over their dedicated interconnects. Pathways makes use of a novel asynchronous distributed dataflow design that lets the control plane execute in parallel despite dependencies in the data plane. This design, with careful engineering, allows Pathways to adopt a single-controller model that makes it easier to express complex new parallelism patterns. We demonstrate that Pathways can achieve performance parity (~100% accelerator utilization) with state-of-the-art systems when running SPMD computations over 2048 TPUs, while also delivering throughput comparable to the SPMD case for Transformer models that are pipelined across 16 stages, or sharded across two islands of accelerators connected over a data center network.

Neural architecture search (NAS) has become an increasingly important tool within the deep learning community in recent years, yielding many practical advancements in the design of deep neural network architectures. However, most existing approaches operate within highly structured design spaces, and hence (1) explore only a small fraction of the full search space of neural architectures while also (2) requiring significant manual effort from domain experts. In this work, we develop techniques that enable efficient NAS in a significantly larger design space. In particular, we propose to perform NAS in an abstract search space of program properties. Our key insights are as follows: (1) an abstract search space can be significantly smaller than the original search space, and (2) architectures with similar program properties should also have similar performance; thus, we can search more efficiently in the abstract search space. To enable this approach, we also introduce a novel efficient synthesis procedure, which performs the role of concretizing a set of promising program properties into a satisfying neural architecture. We implement our approach, αNAS, within an evolutionary framework, where the mutations are guided by the program properties. Starting with a ResNet-34 model, αNAS produces a model with slightly improved accuracy on CIFAR-10 but 96% fewer parameters. On ImageNet, αNAS is able to improve over Vision Transformer (30% fewer FLOPS and parameters), ResNet-50 (23% fewer FLOPS, 14% fewer parameters), and EfficientNet (7% fewer FLOPS and parameters) without any degradation in accuracy.

Multi-Chip-Modules (MCMs) reduce the design and fabrication cost of machine learning (ML) accelerators while delivering performance and energy efficiency on par with a monolithic large chip. However, ML compilers targeting MCMs need to solve complex optimization problems optimally and efficiently to achieve this high performance. One such problem is the multi-chip partitioning problem where compilers determine the optimal partitioning and placement of operations in tensor computation graphs on chiplets in MCMs. Partitioning ML graphs for MCMs is particularly hard as the search space grows exponentially with the number of chiplets available and the number of nodes in the neural network. Furthermore, the constraints imposed by the underlying hardware produce a search space where valid solutions are extremely sparse. In this paper, we present a strategy using a deep reinforcement learning (RL) framework to emit a possibly invalid candidate partition that is then corrected by a constraint solver. Using the constraint solver ensures that RL encounters valid solutions in the sparse space frequently enough to converge with fewer samples as compared to non-learned strategies. The architectural choices we make for the policy network allow us to generalize across different ML graphs. Our evaluation of a production-scale model, BERT, on real hardware reveals that the partitioning generated using RL policy achieves 6.11% and 5.85% higher throughput than random search and simulated annealing. In addition, fine-tuning the pre-trained RL policy reduces the search time from 3 hours to only 9 minutes, while achieving the same throughput as training RL policy from scratch.

Microfluidic biochips or lab-on-a-chip systems are controlled by the actuation sequences designed for some specific bioprotocols. Different attacks specifically, hardware Trojans in diagnostic kits like microfluidic biochips can jeopardize the healthcare industries. As the actuation sequence is also a piece of information, which can be altered by hardware Trojans, man-in-the-middle attacks, etc., it is essential to design a security model with some proper encryption techniques in order to make biochip designs trustworthy. Thus, in this paper, we present a security model for avoiding intellectual property theft of actuation sequences for microfluidic biochips in each stage of the biochip design flow. Furthermore, we describe systematic algorithms to minimize the time requirements for achieving the desired goals so that the chance of an attack is reduced, and hence, to enhance the security concerns of microfluidic biochips. Simulation results demonstrate that the proposed security model leads to maintain the time-to-result while not exceeding the completion time of different bioprotocols. The proposed scheme, which used AES as an encryption algorithm with a 128-bit encryption key, has also shown a speedup of 8.5 (with 88% efficiency) faster than the prior efficient scheme.

Among recent technological advances, microfluidic biochips have been leading a prominent solution for healthcare and miniaturized bio-laboratories with the assurance of high sensitivity and reconfigurability. On increasing more unreliable communication networks day-by-day, technological shifts in the fields of communication and security are now converging. In today's cyber threat landscape, these microfluidic biochips are ripe targets of powerful cyber-attacks from different hackers or cyber-criminals. Hence, securing such systems is of paramount importance. This paper presents the security aspects of digital microfluidic biochip layout to protect the confidentiality of layout data from unscrupulous people and man-in-the-middle attacks. We propose an authentication mechanism with an error control mechanism that provides reliability, authentication, trustworthy and safety for both storage and communication of GDS, i.e., Graphical Design System, file generally used for digital microfluidic biochip layouts. Simulation results articulate the efficacy of the proposed security model without the overhead of the bioprotocol completion time. The proposed scheme, which used AES as an encryption algorithm with a 256-bit encryption key, has also shown a speedup of 6.0 (with 85% efficiency) faster than the prior efficient scheme. We hope to develop a secure layout design flow for biochips to achieve better resistance to any attack.

Being a structure like a two-dimensional (2D) array of microvalves and cells, Programmable Microfluidic Device PMD biochips have the characteristics of reconfigurability and flexibility unlike conventional flow-based microfluidic biochips. In recent years, several design automation techniques for PMD biochips have been reported. For automated control of the PMD chip implementing a bioprotocol, one of the important tasks is to minimize the number of fluid flows for loading the reactant fluids into specific cells before the bioprotocol is executed. In this work we intensively study the fluid loading problem for PMD chips and we propose a two-phase approach to solve this problem. First, we propose a constraint satisfaction problem (CSP) based method, called loading-aware fluid-to-cell assignment (LAFCA) in order to obtain a suitable fluid-to-cell assignment, which will be beneficial for fluid loading phase. Then we propose an exact method, called CSP-based loading algorithm (CSPLA) and a near-optimal heuristic method, called determining flows from the last (DFL), for determining a sequence of fluid flows required to load different fluids into the cells of a PMD chip. We formulate CSPLA as a single objective optimization problem to minimize the total number of flows. For the output as a sequence of fluid flows we define three loading parameters, the total number of flows (K), the total number of 90° bends in all flow paths (B), and the total flow path length (L). Simulation results confirm that LAFCA combined with CSPLA outperforms (K, B and L reduced by 63.9%, 31.7% and 59.9%, respectively) the state-of-the-art method fluid loading algorithm for PMD (FLAP) [Gupta et al., TODAES, 2019]. Whereas, LAFCA combined with DFL can reduce the loading parameters K, B and L by 61.2%, 20.8% and 57.4%, respectively over using only FLAP. Also from the overall simulation results we can conclude that for many testcases, DFL can find the near-optimal Ks.

Silicon photonics (Si-photonics) is a potential technology that integrates the electronic and optical circuits on a single chip, in order to satisfy the increasing demand of high-speed and low-power dissipation in the current very-large-scale integration circuits. It has opened up the research directions in the domain of design automation for photonic integrated circuits. While deciding the physical layout of the optical circuits on the substrate, it is crucial to obtain the optimal routing of optical waveguides. The optical channel routing problem is a multi-objective optimization problem, in which all the parameters like the total bend loss, the total propagation loss, the total crossing loss, and the total number of tracks are required to be minimized. However, in comparison to propagation and crossing loss, the bending loss has a higher impact on the total signal loss. In this paper, a grid-based method has been proposed for optical waveguide channel routing (OWCR) while reducing the total bend loss and the total number of tracks. Simulation results reveals that OWCR can reduce the total bend loss by 25.82% and 36.57% over the state-of-the-art technique for h = 1 and h = 1.732, respectively, while increasing the total number of tracks by 18.68%.

One of the major optimizations employed in deep learning frameworks is graph rewriting. Production frameworks rely on heuristics to decide if rewrite rules should be applied and in which order. Prior research has shown that one can discover more optimal tensor computation graphs if we search for a better sequence of substitutions instead of relying on heuristics. However, we observe that existing approaches for tensor graph superoptimization both in production and research frameworks apply substitutions in a sequential manner. Such sequential search methods are sensitive to the order in which the substitutions are applied and often only explore a small fragment of the exponential space of equivalent graphs. This paper presents a novel technique for tensor graph superoptimization that employs equality saturation to apply all possible substitutions at once. We show that our approach can find optimized graphs with up to 16% speedup over state-of-the-art, while spending on average 48x less time optimizing.

In recent years, silicon photonics (Si-photonics) have received significant attention among researchers due to complementary metal-oxide semiconductor compatibility, and the characteristics of high-speed and low-power dissipation. The integration of electronic and optical circuits on a single chip has opened up new directions of research in the domain of digital logic design and synthesis of photonic integrated circuits (PICs). Several optical switching devices using different technologies have been designed and experimentally demonstrated, which further helps in implementing PICs. In order to efficiently design larger, complex and reliable PICs, the photonic design automation techniques are being explored as electronic design automation techniques have been investigated in case of very large-scale integration circuits. This paper presents an extensive survey of recent work reported in the literature on the domains of logic circuit design, synthesis, and physical design automation for implementing PICs. The aim of this survey is to start with the fundamental optical concepts and then move to the latest research domains of design and synthesis of PICs. Finally, we provide a discussion on the challenges and the future research directions toward practically realizing the Si-photonics and PICs.

Machine learning compilers rely on making optimized decisions in order to generate efficient code for a given computation graph. Many of these decision making processes can be formulated as graph optimization problems. The solution to these graph optimization problems is typically computed based on human designed heuristics. Learning/search-based methods have been recently investigated to improve upon or remove the need of human designed heuristics. However, existing methods that can reliably provide high quality solutions require iterative evaluations on real hardware. The evaluations can be costly especially for large graphs, making these methods infeasible to be deployed in production. To reduce or eliminate the evaluation cost, learning graph optimization strategies that can generalize across graphs is desirable. In this work, we propose learning local advantage functions for generalizable compiler graph optimizations. The learned model can be trained offline with supervised learning on massive amount of training data and then used to guide the search of optimal decisions on previously unseen graphs. We demonstrate the effectiveness of our approach on the operation fusion task and discuss several challenges we encountered in practice.

Microfluidic technologies enable replacement of time-consuming and complex steps of biochemical laboratory protocols with a tiny chip. Sample preparation (i.e., dilution or mixing of fluids) is one of the primary tasks of any bioprotocol. In real-life applications where several assays need to be executed for different diagnostic purposes, the same sample fluid is often required with different target concentration factors (CFs). Although several multi-target dilution algorithms have been developed for digital microfluidic biochips, they are not efficient for implementation with continuous-flow-based microfluidic chips, which are preferred in the laboratories. In this article, we present a multi-target dilution algorithm (MTDA) for continuous-flow-based microfluidic biochips, which to the best of our knowledge is the first of its kind. We design a flow-based rotary mixer with a suitable number of segments depending on the target-CF profile, error tolerance, and optimization criteria. To schedule several intermediate fluid-mixing tasks, we develop a multi-target scheduling algorithm (MTSA) aiming to minimize the usage of storage units while producing dilutions with multiple CFs. Furthermore, we propose a storage architecture for efficiently loading (storing) of intermediate fluids from (to) the storage units.

Runtime and scalability of large neural networks can be significantly affected by the placement of operations in their dataflow graphs on suitable devices. With increasingly complex neural network architectures and heterogeneous device characteristics, finding a reasonable placement is extremely challenging even for domain experts. Most existing automated device placement approaches are impractical due to the significant amount of compute required and their inability to generalize to new, previously held-out graphs. To address both limitations, we propose an efficient end-to-end method based on a scalable sequential attention mechanism over a graph neural network that is transferable to new graphs. On a diverse set of representative deep learning models, including Inception-v3, AmoebaNet, Transformer-XL, and WaveNet, our method on average achieves 16% improvement over human experts and 9.2% improvement over the prior art with 15 times faster convergence. To further reduce the computation cost, we pre-train the policy network on a set of dataflow graphs and use a superposition network to fine-tune it on each individual graph, achieving state-of-the-art performance on large hold-out graphs with over 50k nodes, such as an 8-layer GNMT.