Germanium (Ge) FinFETs with HfOx-based gate stacks are fabricated to study the CMOS applications. To evaluate the logic circuit operation, the associated CMOS inverters are characterized. Compared to the HfO2, the Hf0.5Zr0.5Ox (HZO) gate stack provides higher drive currents and more symmetric Vth behaviors, which should be associated with the polarization effect. Through cyclic voltage transfer characteristic (VTC) operation and systematical analysis, it is found that both polarization and charge trapping in the gate stack impact the device characteristics. The HZO devices show a negative VTC shift with cycling, while the HfO2 devices reveal a positive shift. This opposite VTC behavior for both gate stack schemes indicates that the interaction of interface states and dipoles significantly influences the device operation. The results revealed in this work present a comprehensive understanding of HfOx-based device optimization.

A 5-nm-thick HfO 2 anti-fuse one-time programmable (OTP) memory achieving a record-high pulsed memory window (MW) of $2.1\times 10^{8}$ at a low read voltage (V read ) of 1 V have been proposed and demonstrated for the first time. Furthermore, the HfO 2 OTP memory shows a robust 25°C retention with an extremely stable pulsed MW $> 2\times 10^{8}$ after 10 7 s. From the pulsed characteristics and reliability viewpoints, the HfO 2 OTP memory is a very suitable candidate for the Internet of Things (IoTs) applications and automotive (ATV) security integrated circuits (ICs).

Germanium–tin (GeSn) epitaxy layer was prepared on an 8-in SOI wafer with a Ge buffer layer. The etching rates of different solutions for the GeSn layer were investigated. The ammonia peroxide mixture can remove the Ge buffer layer with high efficiency and selectivity to the GeSn layer. Heated ammonia solution is able to etch the Si layer without damaging the GeSn layer significantly. The two-step etching process developed in this study is conducive to achieving GeSn nanowires (NWs) by selectively etching the Ge buffer and Si bottom layers. GeSn NWFETs were fabricated and measured. The strain of the GeSn NW channels is preserved with the optimized fabrication process proposed in this study.

In this work, multiple-layer stacked gate-all-around polycrystalline silicon (poly-Si) nanosheet channel ferroelectric-Hf x Zr 1-x O 2 (FE-HZO) FETs without and with NH 3 plasma treatment at both the TiN/HZO and ZrO 2 /TiN interfaces were successfully fabricated, and their reliability was investigated and discussed for the first time. The devices after a positive gate bias stress (PGBS) test revealed that the average subthreshold swing (SS) degradation and the threshold voltage shift can be considerably improved by NH 3 plasma treatment at both the TiN/HZO and ZrO 2 /TiN interfaces. Furthermore, the devices after NH 3 plasma treatment show the significantly reduced degradation rates which are related to transconductance, ON-current, and gate leakage current. By using NH 3 plasma treatment at both the TiN/HZO and ZrO 2 /TiN interfaces to significantly enhance the gate-stack quality and effectively suppress the generation of oxygen vacancies and interface traps during the PGBS test, the devices exhibit an excellent SS of 51.4 mV/dec., a high driving current of $49.5 \mu \text{A}/\mu \text{m}$ , and a strong PGBS immunity, making them attractive for monolithic 3-D integrated circuit applications.

In this work, we report ferroelectric HfZrO x (FE-HZO) Ge FinFET inverters fabricated by the low-damage neutral beam etching (NBE) technology. A remarkable voltage gain over 50 V/V is achieved. Cyclic operation of the inverters were performed to investigate the reliability of the devices. The distinct positive and negative shifts of voltage transfer curves are found owing to trap and polarization dominated mechanism, respectively. The findings of this work is conducive to better understanding of operation for ferroelectric-based Ge CMOS.

This study fabricated and verified a germanium (Ge) fin field-effect transistor (FinFET) on developed GeSOI platform. The Ge FinFETs were demonstrated for radio-frequency (RF) applications with a harmonic radar tag. The relation between the detection range (Rd), received power (Pr), and threshold voltage (Vth) of a diode was qualitatively discussed. To meet the requirement of a low Vth, two kinds of Ge FinFETs with different metal gates were fabricated and compared. After the evaluation of electrical characteristics of n-type and p-type Ge FinFETs with different fin numbers, a tag for harmonic radar was designed by integrating diode-connected TiN gate 1-fin Ge FinFETs (Vth = 0.1 V) with a high impedance antenna. The RF performance was evaluated at 9.4 GHz and 18.8 GHz. The results indicated a 50 % improvement in the Rd as compared to the tag using a commercial Schottky diode. Therefore, the proposed low-Vth Ge FinFET on developed GeSOI platform for complementary metal–oxide–semiconductor (CMOS) is promising for high-sensitivity harmonic radar applications.

In this article, heterogeneous complementary field-effect-transistor (CFET) constructed by vertically stacking amorphous indium gallium zinc oxide (a-IGZO) n-channel on poly-Si p-channel with their own dielectric layer and work function metal gate inverters were demonstrated. Meanwhile, high-frequency IGZO radio frequency (RF) devices with poly-Si as guard ring material simultaneously were fabricated in the same process. High ${f}_{\text {T}}$ and ${f}_{\text {max}}$ IGZO Radio Frequency Integrated Circuits (RFICs) with the excellent on–off ratio need to be promoted by introducing fluorine-based gas. For the IGZO device in CFET, its threshold voltage can be tuned by the adjusted gate for ideal inverter operation at different supply voltage ( ${V}_{\text {DD}}$ ). Moreover, the swing of the IGZO transistor and the gain extracted from voltage transfer characteristic (VTC) curves can also be improved when the controlled gate and adjusted gate are connected as an input terminal, but the ${V}_{\text {TH}}$ tunability for the inverter is satisfied in the meantime. We also simulated 6T-SRAM circuit by SPICE model to further investigate the potential of an adjusted gate for optimizing the noise margin during SRAM operation.

This research aims to develop platform for Ge channel CFETs device fabrication. Double or higher density layered Ge film structure is required for Ge channel CFETs. Two different technique is investigated and discussed. Ge/Si/Ge stack epitaxy combined with wet selective etching provides a simplified platform with reasonable cost. While the developed layer transfer process provides higher flexibility and possibility. The combination of different orientation promoting n-type and p-type channel mobility respectively can be realized.

Microwave annealing (MWA) processes were used for the first time to obtain Ti supersaturated Si. High Ti doses were ion implanted on Si substrates and subsequently MWA processed to recrystallize the amorphous layer. The resulting layers were monocrystalline with a high density of defects. Ti depth profiles indicate that diffusion is avoided once recrystallization is produced. Finally, the electronic transport properties measurements point to a decoupling effect between the Si:Ti layer and the substrate. The implanted layer present also a shallow donor and very high Hall mobility.