In complementary metal oxide semiconductor (CMOS) technology, the integration of porous low-k materials becomes mandatory from the 45 nm technological node and beyond in order to reach interconnect performances. As previously described, such porous low-k materials can easily be damaged by all the process steps (especially etching and post-etch treatment processes) that can induce a potential increase in the dielectric constant. In this context, different hard mask strategies such as metallic or organic masks have been proposed for porous SiOCH patterning. Each integration scheme presenting advantages and drawbacks for porous SiOCH film integration is dealt with in this chapter.

For the fabrication of interconnect structures, porous low-k dielectrics are exposed to various plasma processes during etching, during post-etch treatments used to remove carbon-based masks and during treatment surfaces. We will describe here the main plasma processes used for the integration of low-k films, focusing on plasma surface interaction for methylsilsesquioxane (MSQ) films (porous and non-porous SiOCH). When not mentioned, the film is deposited by plasma enhanced chemical vapor deposition (PECVD).

To improve the integrated circuits’ performance and continue the downscaling of dimensions, it is necessary to use low dielectric constant materials as interconnects insulators. Current porous SiCOH low-k dielectrics are now reaching their limits since their porosity enables the diffusion of species that modify the inner surface of the pores. To further reduce the dielectric constant, it is necessary to change paradigm in interconnects fabrication. In this paper, we discuss the most promising innovations in terms of process, materials and architectures to reduce the interconnects insulators dielectric constant.

A loss of silicon in active source/drain regions of CMOS transistors can be observed during nitride spacer etch processes, employing CH3F/O2/He based chemistries in high density plasmas. This phenomenon, the so-called “silicon recess”, is a key criterion for the subsequent steps involved in the transistor fabrication process. In this work, the authors compare two CH3F/O2/He spacer etch processes typically used in industry. The mechanism for high Si3N4/Si selectivity is identified as the creation of a SiOxFy passivation layer, generated at the silicon surface. Using in situ ellipsometry and angle resolved x-ray photoelectron spectroscopy, the authors demonstrate that the oxidized layer which leads to silicon recess is driven by the ion energy. Moreover, in the case of high ion energy processes, implanted carbon has been identified under the SiOxFy passivation layer.

Gate spacers are used in submicron metal oxide semiconductor field effect transistor (MOSFET) engineering in order to precisely define the channel length with abrupt junction geometry and eventually to tailor the electrical characteristics of MOSFET. Therefore, gate spacer etch process is considered to be one of the critical processes of CMOS technologies. The Si3N4 spacer etching process requires a high etch selectivity to Si so that Si3N4 etching can be stopped on Si surface without silicon substrate consumption in source/drain (S/D) regions of the MOSFET transistor. It is known that silicon loss in S/D regions during spacer etching causes substrate bias dependent leakage and etching induced damage in the silicon surface raises the resistance of ultrashallow junctions. However, conventional plasma etch processes are reaching their limits in terms of etch selectivity and profile control at the nanometer scale. In this study, we investigate the potential of pulsed plasma for silicon nitride spacer etching.

The fabrication of interconnects in integrated circuits requires the use of porous low dielectric constant materials that are unfortunately very sensitive to plasma processes. In this paper, the authors investigate the etch mechanism in fluorocarbon-based plasmas of oxycarbosilane (OCS) copolymer films with varying porosity and dielectric constants. They show that the etch behavior does not depend on the material structure that is disrupted by the ion bombardment during the etch process. The smaller pore size and increased carbon content of the OCS copolymer films minimize plasma-induced damage and prevent the etch stop phenomenon. These superior mechanical properties make OCS copolymer films promising candidates for replacing current low-k dielectric materials in future generation devices.

New generation of integrated circuits requires the introduction of ultra low-k dielectric material (k < 2.5) to reduce the RC delay. One of the challenges in integrating these ultra low-k materials is the susceptibility of porous dielectric materials to the post etch resist stripping and residue clean processes. There have been studies comparing the effect of oxidization and reducing chemistries to the ultra low-k materials in a conventional asher [1]. There has also been report on the approach of using directional ashing to avoid damage to the ultra low-k materials [2]. In order to gain further understanding regarding the effect of oxidizing vs. reducing chemistries, ion vs. radicals, pressure and temperature to the low-k materials (both dense and porous), we have started a comprehensive study to find answers to these questions. This paper is to report our initial data from this effort.