WSPC Series in Advanced Integration and PackagingEmbedded Cooling of Electronic Devices, pp. 311-331 (2024) No AccessChapter 8: Monolithic Microfluidic Cooling Using Micropin-Fin Arrays for Local High Heat Flux Remediation: Design Considerations, Experimental Validation, and FPGA IntegrationThomas Sarvey, Ankit Kaul, and Muhannad S. BakirThomas SarveyDepartment of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA, Ankit KaulDepartment of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USA, and Muhannad S. BakirDepartment of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, Georgia, USAhttps://doi.org/10.1142/9789811279379_0008Cited by:0 (Source: Crossref) PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail Abstract: With an increase in microelectronic system density, using conventional technologies for cooling continues to become more challenging and is often a limiter of performance and efficiency. One key challenge is to address high background heat fluxes generated across entire chips and packages while mitigating localized hotspots with even higher heat fluxes. In this chapter, cooling of integrated circuits with non-uniform power maps using non-uniform micropin-fin heat sinks is investigated. Two heterogeneous micropinfin samples were fabricated, and single-phase experiments with deionized water were performed to investigate the effectiveness of local micropinfin clustering for hotspot cooling. Large background heat fluxes (250 W/cm2) were cooled in conjunction with even higher hotspot heat fluxes (500 W/cm2), with the lowest achieved average junction-to-inlet thermal resistance (Rth) of 0.092°C/W. Subsequently, to demonstrate the benefit of microfluidic cooling on active silicon, a micropinfin heat sink was etched into the bulk of an Altera Stratix-V field-programmable gate array (FPGA) built using a 28 nm CMOS process. With a benchmark pulse compression algorithm running on the FPGA, thermal and electrical measurements were made. Deionized water was used as a coolant, with flow rates ranging from 0.15 to 3.0 mL/s and inlet temperatures ranging from 21°C to 50°C. An average junction-to-inlet thermal resistance of 0.07°C/W or a heat transfer coefficient of 1.59 × 104 W/m2 °C was achieved. Keywords: Bosch processdeep reactive ion etching (DRIE)hotspotmicrofluidic coolingmicropin-finfield-programmable gate arrays (FPGAs)high-performance computing (HPC)microfluidic coolingthermal management FiguresReferencesRelatedDetails Recommended Embedded Cooling of Electronic DevicesMetrics History KeywordsBosch processdeep reactive ion etching (DRIE)hotspotmicrofluidic coolingmicropin-finfield-programmable gate arrays (FPGAs)high-performance computing (HPC)microfluidic coolingthermal managementPDF download

Heterogeneous integration techniques such as 2.5-D system-in-packages (SiPs) present new challenges that include higher aggregate package power as well as increased thermal crosstalk between different chiplets due to their proximity. This creates the need for advanced cooling solutions uniquely catered to these issues. This work presents the first demonstration of monolithic microfluidic cooling of active 2.5-D ICs to mitigate high-power and thermal crosstalk between chiplets. A 2.5-D FPGA package is used for demonstration purposes. Micropin-fin heat sinks etched directly into the backside of five chiplets in the package are supplied with de-ionized water as coolant through 3-D printed manifolds. This approach helps create a low-form factor cooling solution. Design considerations for the polymer manifold as well as micropin-fin etching are discussed. FPGA core temperature was maintained at approximately 30 °C when dissipating nearly 107 W of power, corresponding to a thermal resistance of 0.074 °C/W, and thermal coupling values as low as 0.010 °C/W. We also demonstrate excellent thermal performance even with elevated inlet temperatures for energy-efficient cooling applications.

Single-phase liquid cooling in microchannels and microgaps has been successfully demonstrated for heat fluxes of similar to 1 kW/cm(2) for silicon chips with maximum temperature below 100 degrees C. However, effectively managing localized hotspots in heterogeneous integration, which refers to the integration of various components that achieve multiple functionalities, entails further thermal challenges. To address these, we use a nonuniform pin-fin array. Single phase liquid-cooling performance of four silicon test chips, thermal design vehicles (TDVs), each with a nonuniform pin-fin array, are experimentally examined. We evaluate multiple combinations of hotspot and background heat fluxes using four background heaters aligned upstream to downstream, and one additional hotspot heater located in the center. We examine the thermal performance of cylindrical fin-enhanced TDVs and hydrofoil fin-enhanced TDVs, both with two designs: one with increased fin density around the hotspot only, and another with increased fin density spanning the entire width of the channel. The resulting heat flux ratio of the localized hotspot to background heaters varies from 1 to 5. TDVs with spanwise increased hydrofoil fin density (spanwise hydrofoil) exhibit the best thermal performance with 6% to 14% lower hotspot temperature than others. TDVs with spanwise increased cylindrical fin (cylindrical spanwise) maintain a balance between hotspot cooling performance and pressure drops. In general, as the temperature of the hotspot remains around 70 degrees C with a heat flux of 625 W/cm(2), the nonuniform fin-enhanced microgaps appears to be a promising hotspot thermal management approach. The pressure drop of hydrofoil spanwise chip is highest among all the cases.

In this paper, we evaluate the use of silicon microfluidic cooling in conjunction with 3D printing techniques to create an ultra-low profile cooling system tailored for 2.5D packages. We present the thermal challenges in 2.5D devices including higher aggregate package power and thermal coupling, and use finite volume and finite difference modeling to demonstrate both thermal and electrical benefits of implementing a microfluidic cooling solution. A field-programmable gate array (FPGA) package with five discrete dice is used as the test vehicle for experimental demonstration. Two discrete implementations of the microfluidic heat-sink are demonstrated: an attached silicon cooler where micropin-fin heat-sink is etched on a separate piece of silicon, and a monolithic cooler with the micropin-fins etched directly into the backside of the dice. Both are capped with low-profile 3D printed fluid delivery manifolds. We demonstrate very low junction-to-inlet thermal resistance values of 0.094 °C/W with the attached microfluidic silicon cooler and 0.074° C/W with the monolithic heat sink for the FPGA core die.

It is agreed that air-cooled heat sink (ACHS) would become incapable of 3-D integrated circuits (ICs). A switch from ACHS to a microfluidic heat sink (MFHS) is believed to be a promising solution. Tier-specific MFHS, where the flow rate of each tier can be controlled independently, has been further proposed in consideration of the power consumptions of pumps. However, these works are generally based on a steady power map, which in reality is mostly time-dependent. In this paper, a machine learning (ML)-based control method, combining the Bayesian optimization (BO) and the artificial neural network (ANN), is applied to 3-D ICs with the tier-specific MFHS, considering a time-dependent power map. BO is first applied because it has been demonstrated to outperform other state-of-the-art black-box optimization techniques due to its quick converge. However, as more and more data are acquired when the system keeps working, its computational time increases sharply due to the increasing calculation complexity, which cannot be accepted as we aim for dynamic thermal management. Therefore, ANN is then applied. With the online learning method, its calculation complexity remains constant as more data are acquired. Because of this, its time consumption remains small as the system keeps working. Results of the flow rates and the temperatures are finally presented, which prove that with the ML-based control method, power consumptions of the pumps are intelligently saved while, at the same time, the temperature constraints are met.

The 2.5-D integration is becoming a common method of tightly integrating heterogeneous dice with dense interconnects for efficient, high-bandwidth inter-die communication. While this tight integration improves performance, it also increases the challenge of heat extraction by increasing aggregate package powers and introducing thermal crosstalk between the adjacent dice. In this article, a microfluidic heat sink is used to cool a 2.5-D Stratix 10 GX field-programmable gate array (FPGA) consisting of an FPGA die surrounded by four transceiver dice. The heat sink utilizes a heterogeneous micropin-fin array with micropin-fin densities that are tailored to the local heat fluxes of the underlying dice. Enabled through a 3-D printed enclosure for fluid delivery, the assembled heat sink has a total height of 6.5 mm, including the tubes used for fluid delivery. The heat sink is tested in an open-loop system with deionized water as a coolant, and thermal performance is compared against a high-end air-cooled heat sink. Improvements in die temperatures, computational density, and thermal coupling between the dice are observed. The effect of the FPGA power on the surrounding transceiver die temperatures was reduced by a factor of ${10}\times$ to over ${100}\times$ when compared with the air-cooled heat sink.

2.5 dimensional stacked integrated circuits (2.5D-SICs) with through-silicon vias (TSVs), as next generation silicon technologies, are promising to go beyond Moore's law for compact, high-performance, energy-efficient microsystems. 2.5D-SICs with closely placed heterogeneous dies are considered a first step towards full 3D integration. In this paper, a novel micro-channel dielectric coolant manifold for 2.5D-SICs with multiple high-power dies, has been investigated. Five active dies are modeled with power maps of one 50 W, 25 mm×25 mm field programmable gate array (FPGA), and four high heat flux transceivers (30 W/each, 6 mm×6 mm/each). In order to provide thermal management to this heterogeneous chip system, micro-fin-bridges and micropins have been implemented in the manifold. In addition, all dies have been immersed in the micro-channel with dielectric coolant to isolate the thermal interaction between dies. Effects of chips' placement, dimensions of micro-fin-bridges and micro-pins, and dielectric coolant supply and removal locations within the manifold on pressure drop and heat transfer have been parametrically studied by full-scale computational fluid mechanics/heat transfer simulations.

As microelectronic system density continues to increase, cooling with conventional technologies continues to become more challenging and is often a limiter of performance and efficiency. The challenge arises due to both large heat fluxes generated across entire chips and packages, and localized hotspots with even higher heat flux. In this paper, nonuniform micropin-fin heat sinks are investigated for the cooling of integrated circuits with nonuniform power maps. Four heterogeneous micropin-fin samples were fabricated and tested in single-phase experiments with deionized water to investigate the effectiveness of local micropin-fin clustering for the cooling of hotspots. Cylindrical and hydrofoil micropin-fins were tested, as well as two types of heterogeneous arrays: those with pin-fins clustered directly over the hotspot and those with the high density cluster spanning the entire width of the channel to prevent flow bypass around the cluster. Samples were tested with a uniform nominal heat flux of 250 W/cm2 as well as a hotspot heat flux of 500 W/cm2. Local micropin-fin clustering was found to be an effective method of reducing local thermal resistance with a modest pressure drop penalty.

Understanding two-phase convective heat transfer under extreme conditions of high heat and mass fluxes and confined geometry is of fundamental interest and practical significance. In particular, next generation electronics are becoming thermally limited in performance, as integration levels increase due to the emergence of 'hotspots' featuring up to ten-fold increase in local heat fluxes, resulting from non-uniform power distribution. An ultra-small clearance, 10 mu m microgap, was investigated to gain insight into physics of high mass flux refrigerant R134a flow boiling, and to assess its utility as a practical solution for hotspot thermal management. Two configurations - a bare microgap, and inline micro-pin fin populated microgap - were tested in terms of their ability to dissipate heat fluxes approaching 1.5 kW/cm(2). Extreme flow conditions were investigated, including mass fluxes up to 3000 kg/m(2) s at inlet pressures up to 1.5 MPa and exit vapor qualities approaching unity. Dominant flow regimes were identified and correlated to two phase heat transfer coefficients which were obtained using model based data reduction for both device configurations, The results obtained were compared to predictions using correlations from literature, with the maximum heat transfer coefficient reaching 1.5 MW/m(2) K in the vapor plume regime in the case of the finned microgap. (C ) 2016 Elsevier Ltd. All rights reserved.

In this paper, 2.5-D integrated circuits (ICs) using bridge-chip technology are thermally evaluated to investigate thermal challenges and opportunities for such multidie packages. To this end, the objectives of this paper are twofold. First, thermal benchmarking of a number of 2.5-D integration approaches is performed and compared to 3-D ICs for completeness. Thermal modeling shows that the evaluated 2.5-D integration approaches exhibit similar thermal characteristics, but show significant improvements compared to 3-D IC solutions with the same power consumption. Second, this paper explores bridge-chip-based 2.5-D integrated systems as a function of bridge-chip thickness, thermal interface material properties, microbump properties, die thickness, die thickness mismatch, and die-to-die spacing along with transient analysis to investigate time-domain thermal coupling. Results suggest that a die thickness mismatch of 100 mu m can increase the maximum temperature by 25.8% Therefore, the die thickness mismatch should be kept as small as possible, and the hottest die should be the thickest. Moreover, reducing die-to-die space from 1 to 0 mm increases thermal coupling, and the low-power dice, such as DRAM, can have a temperature increase of 6.1%.

Single-phase liquid cooling in microchannels and microgaps has been successfully demonstrated for heat fluxes of ~1 kW/cm 2 in Si components. Surface area enhancements such as uniformly distributed pin-fin arrays can provide further improvements in cooling performance. However, effectively managing localized hot spots in heterogeneous integration (HI), which refers to the integration of various components that achieves complex functionalities, entails a thermal challenge. Here we address this thermal challenge of HI by using nonuniform pin-fin array-enhanced microgap liquid-cooling. This paper tests the liquid-cooling performance of four test device vehicles (TDVs), each with a pin-fin-enhanced microgap with non-uniform fin arrays. Multiple combinations of hot spot and background heat fluxes are evaluated. Nonuniform heating conditions were created using four background heaters located from the upstream to the downstream, and one additional hotspot heater located in the center. Thermal performance of cylindrical fin-enhanced TDVs and hydrofoil fin-enhanced TDVs are examined. Both have two designs: one with increased fin density around the hotspot only, and another with increased fin density along the spanwise direction. Deionized (DI) water is the coolant for all test cases, with heat flux varying from 125 W/cm 2 to 625 W/cm 2 for the hotspot, and 125 W/cm 2 to 250 W/cm 2 for background heaters. The resulting heat flux ratio of the localized hotspot to background heaters varies from 1 to 5. The TDVs of the spanwise-increased hydrofoil fins exhibited the best thermal performance-6% to 14% lower hotspot temperature than others. The TDVs of the spanwise-increased cylindrical fins maintain a balance between hotspot cooling performance and pressure drop. In general, as the temperature of hotspot remains around 70°C with a heat flux of 625 W/cm 2 , the non-uniform fin-enhanced microchannel-cooling technology appears to be a promising hotspot thermal management approach under moderate background heat flux.

Microfluidic cooling has been demonstrated as an effective means of cooling microelectronic circuits with a very low convective thermal resistance and potential for integration in close proximity to the area of heat generation. However, microfluidic cooling experiments to date have been limited to silicon with resistive heaters representing the heat generating circuitry. In this paper, a micropin-fin heat sink is etched into the back side of an Altera Stratix V field-programmable gate array (FPGA), built in a 28-nm CMOS process. Thermal and electrical measurements are made running a benchmark pulse compression algorithm on the FPGA. Deionized water is used as a coolant with flow rates ranging from 0.15 to 3.0 mL/s and inlet temperature ranging from 21 degrees C to 50 degrees C. An average junction-to-inlet thermal resistance of 0.07 degrees C/W is achieved.

We present an experimental study of two phase flow of refrigerant R245fa in a pin fin enhanced microgap for a range of heat fluxes between 151 W/cm 2 to 326 W/cm 2 . The gap has a base surface area of 1cm × 1cm and height of 200 μm. An array of hydrofoil shaped pin fins covers from bottom to top of the microgap. The pin fins have chord length, longitudinal pitch, and transversal pitch of 75μm, 450μm and 225μm, respectively. On the back side of the chip, four platinum heaters are fabricated and electrically powered in series to enable two phase flow in the microgap, which was part of a pumped flow loop. Heater and surface temperature data were obtained versus heat flux dissipated. Flow visualization was performed using a high speed camera in the heat flux range from 151 W/cm 2 to 326 W/cm 2 . The amount of heat loss across the test section is also provided.

This paper reports on novel thermal testbeds with embedded micropin-fin heat sinks that were designed and microfabricated in silicon. Two micropin-fin arrays were presented, each with a nominal pin height of 200 μm and pin diameters of 90 μm and 30 μm. Single-phase and two-phase thermal testing of the micropin-fin array heat sinks were performed using de-ionized (DI) water as the coolant. The tested mass flow rate was 0.001 kg/s, and heat flux ranged from 30 W/cm2 to 470 W/cm2. The maximum heat transfer coefficient reached was 60 kW/m2 K. The results obtained from the two testbeds were compared and analyzed, showing that density of the micropin-fins has a significant impact on thermal performance. The convective thermal resistance in the single-phase region was calculated and fitted to an empirical model. The model was then used to explore the tradeoff between the electrical and thermal performance in heat sink design.

This paper demonstrates the integration of microfluidic cooling for thermally limited 3-D microsystem applications. Thermal modeling of logic and memory dice on a silicon interposer is presented under air and microfluidic cooling conditions. Moreover, the electrical characteristics of micropin-fin-embedded through silicon vias (TSVs) immersed in deionized (DI) water are investigated through high-frequency measurements. The TSV capacitance and conductance are extracted from the measurements. The measurement results show that the capacitance and conductance of the TSVs increase as the micropin-fin diameter decreases at a fixed TSV pitch at high frequencies.

There are a number of emerging electronic applications that are thermally limited and may exhibit high overall power dissipation ("background") combined with local very high power fluxes ("hotspot"). We have batch fabricated a microfluidic heat sink specifically designed to address both levels of heat removal. A microgap for hotspot cooling and micropin-fins are sequentially deep etched in a silicon substrate. The combined microfluidic heat sink is sealed by bonding another layer of silicon to the substrate. The coolant is injected into the combined heat sink from two distinct ports to dissipate the generated heat by micro-heaters. These micro-heaters emulate hotspot and background heat generation by active circuits as well as enable chip junction temperature measurement. Mechanical modeling is conducted to verify the reliability of the design and assess limits on the operating pressure of the fabricated system.

This paper proposes a thermal isolation technology using air gap and mechanically flexible interconnects (MFIs) for heterogeneous 3-D integration. Thermal modeling shows that the proposed architecture achieves a temperature reduction of approximately 40.0% in the low-power tier compared to conventional approaches using microbumps and underfill. To demonstrate the technology, a two-tier testbed is fabricated, assembled and tested. The experimental results of test cases show an average temperature reduction of approximately 30.0% in the low-power tier.

The presence of variable heat fluxes, such as localized hotspots in integrated circuit (IC) architectures poses a key challenge for thermal management of existing (2D) and emerging three-dimensionally (3D) stacked chips. The use of conventional microchannel or uniform pin fin arrays for microfluidic cooling do not provide adequate surface area for heat transfer in the vicinity of regions of concentrated high power (hotspots), and therefore significant temperature gradients might arise in such zones. In the present investigation, the concept of using a single microfluidic loop for the combined and efficient cooling of hotspot and moderate power (background) areas is proposed, experimentally demonstrated, and supported by a comprehensive numerical model. Two different thermal device vehicles (TDVs) are considered for a range of operating conditions, in which the surface area is locally increased by clustering a dense array of pin fins in the hotspot region for one configuration, while for the other the clustering is uniform in the spanwise direction. De-ionized (DI) water is used as the coolant through a silicon (Si) microgap with 200 tm spacing; the hotspot heat flux is varied from 250 to 750 W/cm(2), while the background heat flux is fixed at 250 W/cm2. Results indicate the capability of the proposed designs to keep the maximum temperature of the combined device below 65 degrees C for an inlet water temperature of 21.3 degrees C, with moderate temperature gradients and pressure drop. In addition, a robust computational fluid dynamics/heat transfer (CFD-HT) model capable of predicting spatially resolved temperature fields arising from heterogeneous heating is validated with relevant experimental data. Detailed benchmark simulations are provided, so they can be reproduced and used for reference in numerical studies with variable pin fin densities. The described methodology represents a cost-effective thermal modeling technique that may be applicable to virtually any type of heat flux distribution or power map, and IC architecture. (C) 2016 Elsevier Ltd. All rights reserved.