We demonstrate growth of SiCP film on Si(110) substrates with excellent structural quality, based on X-Ray Diffraction, Cross-sectional Transmission Electron Microscopy and Secondary Ion Mass Spectrometry analysis. This (110) surface orientation is very important since it represents the sidewall of recessed Source/Drain (S/D) areas when the film is used as an embedded stressor to induce uniaxial tensile strain in a planar transistor. An optimized (110) SiCP growth process can also be used to thicken the S/D regions of non-planar multi-gate device structures (e.g. Fin Field Effect Transistors, Tri-gate FETs) with a highly doped epitaxial film in order to enable good electrical contacts and/or induce strain. The films have been grown using Si3H8, SiH3CH3 and PH3 for growth and Cl2 as the etchant gas, all in inert carrier gas. H2 has been eliminated, preventing Cl2 from reacting with H2 yielding HCl, since Cl2 is needed to establish selectivity. We present trends on temperature, total pressure, SiH3CH3, PH3 and Cl2 etch flow. We studied selective epitaxial growth (SEG) in the 525–575°C range. Thanks to the use of Si3H8 we can obtain high SEG rates even at 525°C in conjunction with a high deposition pressure of 20 kPa (~150Torr). It is observed that the growth rate, carbon concentration, phosphorous concentration and etch rate of SiCP on Si (110) differs greatly from that on Si (100). A process optimized specifically for Si(100) surfaces may yield no growth on Si(110) surfaces. However, optimizing a process on Si(110) is assured to result in growth on Si(100). Comparing one process optimized on Si(110) with the results on Si(100), we found a substantially lower SEG rate, higher [P] incorporation and lower [C] incorporation on Si(110). One key criterion for growth on patterned substrates with Si(110) sidewalls is that the SEG rate on the sidewall must be≥0; otherwise the vertical sidewall will be etched and undercut of the spacer will occur, degrading the structural quality of the transistor and potentially impacting the electrical performance of the device.

In this paper we demonstrate a Si3H8/SiH3CH3/PH3/Cl2 based co-flow process and a “hybrid” co-flow process with interruptions of the deposition. The motivation for the work stems from the desire to improve manufacturability through higher growth rates and higher etch rates commensurate with the drive to lower thermal budgets of integration of Complementary Metal Oxide Semiconductor and memory platforms. For high volume manufacturing, high selective epitaxial growth rates are necessary for enhanced throughput and low cost of ownership. Both high growth rate and low temperatures enable sufficiently high substitutional carbon levels [C]sub in dilute Si:C alloys. The hydride deposition gases Si3H8, SiH3CH3 and PH3 and the etch gas Cl2 were kept separate in the pressurized gas supply lines and injected separately into the reaction chamber thus avoiding premature chemical reactions. The importance and the role of a suitable inert carrier gas are emphasized.

In the present paper we discuss an alternative pre-epi clean method, which is performed at a reduced temperature of 600ºC, while maintaining SiO2 removal efficiency of the conventional H2 pre-epi bake at 800-900ºC. It is essentially an ex-situ HF-dip followed by a GeH4-enhanced Si etch that is performed in-situ in an epi reactor. The etch process lifts-off residual SiO2 together with a very thin well controlled top layer of crystalline Si. An optimal combination of 1.5-1.6nm loss and O, C - free interface has been demonstrated on bare (100) Si wafers. Defect-free substrate-epi interface was verified by photoluminescence study. The amount of removed Si was found to depend on crystal orientation of exposed Si surface, (110) Si being etched ~3x faster than (100) Si. Therefore the method needs to be carefully optimized for devices with various surfaces exposed simultaneously.

In this work, we demonstrate substitutional phosphorus concentration as high as 12 at.% in epitaxial silicon. It is observed that 10 at.% substitutional phosphorus doping is equivalent in tensile strain to incorporating 2.1 at.% substitutional carbon into the silicon lattice. Phosphorus doping of this order produces tensile strain levels suitable for n-channel metal-oxide semiconductor field-effect transistor uniaxial stressor applications. This work focuses on the experimental and theoretical analyses of phosphorus doped silicon based on high resolution X-ray rocking curves, secondary ion mass spectroscopy, Rutherford backscattering spectroscopy, and molecular dynamic modeling.

InAsxPi.x/InP (10 period 50/100Å with x=0.25-0.79) pseudomorphically strained multiple quantum wells (SMQWs) were grown by gas source molecular beam expitaxy (GSMBE) at 470°C and characterized by cross-sectional transmission electron microscope (XTEM), double crystal x-ray diffraction (DCXRD), and optical spectroscopy. The structural analysis demonstrates that excellent control of the sharp interface and limited As-P interdiffusion can be achieved by GSMBE growth. XTEM images of these SMQWs display no misfit dislocations, and DCXRD scans reveal high order superlattice satellite peaks. Photoluminescence (PL) and transmission measurements were performed for all SMQWs to evaluate crystal quality. Only slight degradation in luminescence was observed as the As composition increased. Based on the three-band Kane model which includes the lattice strain, the transition energies of SMQWs were calculated using the conduction-band offset (Qc=δEc/δEg) as an adjustable parameter. The best fit of measured and calculated interband transition energies suggests that Qc is independent of As composition and is 0.70±0.05. Finally, a growth kinetics model based on the Langmuir equation was derived to realize the As/P incorporation ratio in the InAsP materials. Theoretical results show good agreement with experimental data.

We present a catalyst enhanced etch process with high etch rates for amorphous Si based alloys (e.g. α-Si, α-Si:C, α-Si:P, α-SiCP) and low etch rates for crystalline Si (e.g. c-Si, c-Si:C, c-Si:P, c-SiCP) with etch rate ratios up to ~200. The addition of a suitable surface catalyst such as Ge (e.g. from GeH4) during HCl based etch processes increases both, the etch rate of amorphous Si alloys and the etch rate selectivity against c-Si alloys. The Ge source dynamically forms a SiGe surface layer during the etch process. Ge penetrates fast into α-Si through diffusion, forming an α-SiGe film with high [Ge] concentration. Ge diffusion into c-Si however is very limited; a rather slow surface-sub-surface exchange reaction (segregation) causes a penetration depth of only one monolayer. Repeated cycles of a selective chemical vapor etch process following a non-selective deposition process enable effective selective epitaxial growth.

In this paper we demonstrate the successful integration of in-situ doped Si:P epitaxially grown into the source/drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process employing a Si3H8/PH3/Cl-2 based chemistry. A distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We report on material characterization results of the Si: P selective epitaxial growth (SEG). An optimized Si:P SEG process with a SEG rate of similar to 25 nm/min enables a 80-170s short deposition for typical epitaxial layers (35-70 nm), well suitable for high volume manufacturing (HVM). By integrating an isothermal in-situ removal of Si0.65Ge0.35 (protecting/covering the NMOS areas) with a high etch rate selectivity against the underlying thin SOI at process temperature allows to eliminate the in-situ H-2 prebake and the cool-down to process temperature, significantly reducing recipe overhead and the need for a separated, dedicated pre-clean module.

An empirical study of the selective vapor phase epitaxy kinetics of silicon germanium (Si1−xGex) alloys is developed with no assumption on an atomistic mechanism. The growth kinetics are approached efficiently with a power rate law. Partial reaction orders are identified for GeH4, HCl and B2H6 precursors. A trend analysis of the partial reaction order highlights the fine characteristics of the Si1−xGex growth kinetics. The power rate law evidences clearly the competition interactions between Si, Ge and B. Furthermore, a partial derivative study of the power rate law enabled an accurate sensitivity analysis of the selective process.

This work describes using metal-organic chemical vapor deposition (MOCVD) to directly deposit III-V materials on Si/Ge-based substrates, with the primary focus being the methodology used to develop a manufacturable heterointegration process.

This paper presents an empirical study of silicon germanium (SiGe) stressor stability with respect to misfit dislocation nucleation. The relevance of the experimental process parameter set for Si1−xGex selective epitaxy growth is validated by measuring the resultant p-channel Metal Oxide Semiconductor Field Effect Transistor device performances. Electrical performances of devices are correlated with SiGe material stability, in particular to misfit dislocation nucleation. A linear improvement of ION with the recess depth is observed for the 20% Ge split, thus suggesting dislocation free devices. The highest on-state current improvements have been obtained for the 30at.% Ge split.

This paper presents an integrative application of several numerical analytical techniques and associated analysis tools for design optimization and damage prediction in electronics packages and microsystems. This design-for-reliability approach is based on four different types of numerical techniques that allow (1) high-fidelity modelling, (2) reduced order modelling, (3) numerical optimization and (4) uncertainty analysis. The capabilities and the characteristics of the methods that underpin these four types of modelling and analysis tools are firstly investigated. The integration of the methods and tools is then examined and a methodology for coupling the tools in an optimization process is proposed. This numerical methodology involves the following steps: (1) Define sampling points for the design of interest by design of experiments (DOE) and calculate the design response at each DOE point using high-fidelity analysis; (2) construct reduced order models (ROM) for fast analysis using the obtained response values at the DOE points; (3) Undertake deterministic optimization in the defined design space by ROM; and (4) Probabilistic optimization by including variation and uncertainty of the design in the optimization task. This approach is suitable to address design-for-reliability requirements at early design stages in a wide range of application areas. The application of this approach is demonstrated in a case for minimizing the thermal fatigue damage of flip-chip solder interconnects. Design modifications show that this approach can provide improved reliability of the package and in the same time satisfy a number of design requirements.

In this paper we report on electrical demonstration of thermally stable Ni silicides. It has been shown that when a sacrificial Si1−xCx epilayer is grown in the source-drain areas of NMOS transistors prior to silicidation, Ni silicides can withstand a 30min anneal at 750°C and demonstrate excellent electrical performance. We have observed carbon segregation at the NiSiC/Si1−xCx interface which can explain the increased NiSiC thermal stability. We have experimentally demonstrated feasibility of CMOS device implementation of thermally stable Ni silicides.

In this paper we will discuss non-traditional chemical precursors for carbon-doped silicon (Si:C) that enable improved manufacturability through higher growth rates and new deposition temperature regimes commensurate with the drive to lower thermal budgets of integration of CMOS and DRAM platforms. Among the silicon precursors to be discussed are dichlorodisilane (Si2Cl2H4), dichlorosilane and Silcore® (Si3H8). New carbon precursors disilylmethane ((SiH3)2CH2) and propylene (C3H6) are discussed and compared with conventional monomethylsilane (SiH3CH3). For high volume manufacturing, high selective epitaxial growth rates are necessary for high throughput and low cost of ownership. Both, high GR and low temperatures enable high substitutional carbon levels [C]sub in dilute Si:C alloys. Advantages and disadvantages of different Chemical Vapor Deposition (CVD) strategies such as a co-flow process, a Cyclic Deposition/Etch (CDE) process and a “hybrid” process are discussed.

A study is made of the impact of embedded epitaxial Si:C source/drain regions on the DC and low-frequency (LF) noise characteristics of nMOSFETs with 1.4 nitrided oxide gate dielectric. It is shown that a ~10% improvement in ION is achieved for a C concentration of 1%, with not much further improvement going to 1.5%. At the same time, no change of the 1/f noise is observed, indicating that the gate stack integrity is preserved throughout the Selective Epitaxial Growth process.

The selective vapor phase epitaxy (SVPE) kinetics of a Si1−xGex heterostructure is complex. To date, operational kinetics schemes are not available and reactant interactions are not very well understood. This study is a phenomenological investigation of epitaxial film growth rate (GR) and composition. An empirical model is developed specifically to address the kinetics of industrial SVPE processes performed at a pressure above 1Torr. The response function investigated in this study is very similar to the one applied in the field of heterogeneous catalysis. The relevance of a power rate law (PRL) to Si 1−xGex SVPE is assessed with the goodness of fit as well as with a consistency check of the fitting parameters with the chemistry of the process. Despite the lack of a reaction scheme supporting the PRL, trends consistent with the known chemistry of growth kinetics are evidenced, thus confirming the soundness of the method. Partial reaction orders are identified for HCl, SiH2Cl2, GeH4 and B2H6.

The purpose of this paper is to evaluate the impact of the geometry of embedded Si1−xGex source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si1−xGex alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.

In this paper we demonstrate the successful integration of in-situ doped embedded Si:C stressors epitaxially grown in the source and drain areas of nMOS devices using a novel Cyclic Deposition Etch (CDE) process. These layers have substitutional C content ranging between 1% and 2% with potential of achieving even higher substitutional carbon concentration. Another distinctive feature of this process is that it allows for high in-situ P doping for ease of integration within a CMOS platform. We demonstrate superior performance of strained nMOS devices with embedded Si:C showing up to 12.5% on-state current improvement over the unstrained reference process. We report on material characterization results of embedded Si:C stressors, in particular, strain retention properties as a function of subsequent post-epitaxy processing.