With technology scaling of embedded nonvolatile memories, voltage scaling below 12 V is a primary goal to maintain the area efficiency of the memory module. The SONOS technology shows promise as a technology for present and future low voltage memory cells. This paper examines the physics of scaled SONOS gate dielectrics in relation to reducing the operational voltage. In particular, we have examined the influence of tunnel oxide, nitride and top oxide thicknesses. The results are supported by electrical simulation of the SONOS gate dielectric. By properly scaling the dielectric films and utilizing electrical simulation we have determined a limit for scalability of the SONOS technology in terms of operation voltage.

A dual hard mask concept for high resolution patterning has been evaluated with focus on highly selective etching processes for semiconductor manufacturing. The integration of thin SiO2 and ZrO2 hard mask materials enables highly selective patterning via plasma etch processes for future technology nodes. The patterning sequence is demonstrated for hole arrays with sizes down to 25 nm using a 50 nm thin resist which leads to the fabrication of trenches in silicon with aspect ratios up to 20:1. Alternative ZrO2 based materials were investigated with focus on surface roughness reduction since it influences the final line edge roughness (LER). Here Si-doped ZrO2 (ALD) was compared to the undoped and crystalline ZrO2 as main selective material.

Program disturb may ultimately limit the scalability of modern NAND flash memory technologies and is typically most serious for the memory cells neighboring the string select transistors. The feasibility, accuracy, and predictive capability of a new advanced physical simulation model for the program disturb in NAND flash memories is demonstrated by means of a comprehensive experimental verification based on a 48 nm TANOS technology. For the first time it is demonstrated that the dependence of program disturb on the distance between the memory cells and the select transistors can be accurately modeled by a physical model without fitting any model parameter.

In this work it is shown that film stress in the gate stack of TANOS NAND memories plays an important role for cell device performance and reliability. Tensile stress induced by a TiN metal gate deteriorates TANOS cell retention compared to TaN gate material. However, the erase saturation level as well as cell endurance is improved by the use of a TiN gate. This trade-off between retention and erase saturation for TANOS cells is elaborated in detail.

The hot electron induced mechanism disturbing the stored information in inhibited bit lines during the programming of nonvolatile memories with NAND architecture is studied in detail using a new dedicated advanced physical simulation scheme for the first time.

Light emitting field effect transistors based on narrow layers of silicon nanocrystals (NCs) in the gate oxide were fabricated. Direct quantum mechanical electron and hole tunneling into NCs was achieved by self-alignment of NCs-interface-distances to ∼2 nm. The direct tunneling reduces oxide degradation, prolongs device lifetime and increases operation speed. Self-alignment occurs during thermal treatment of ion irradiated stacks of 50 nm polycrystalline silicon/15 nm SiO2/(001)Si substrate. An alternating voltage (ac) was applied to the gate to inject charges into the NCs. Due to injection by direct tunneling, electroluminescence extends to higher ac frequencies than reported so far.

Current-voltage characteristics were measured, electrically modeled, and calculated for gate oxides, which contain nanocrystals (NCs) in different distributions, sizes, and densities. Ge and Si NCs were synthesized embedded in separate thin SiO2 layers by ion implantation at different fluences and subsequent annealing. It was found that the currents through the NC containing thin gate oxides are strongly related to the NCs’ location and are not driven by ion implantation induced oxide defects. Charging of the NCs determines the internal electrical fields, which is confirmed by simultaneous current and capacitance measurements. Depending on the implanted fluence the Ge NCs were mainly detected in the oxide center or close to the Si/SiO2 interface. The Si NCs were fabricated in the oxide center sandwiched between two oxide regions denuded of NCs. The processes of Si NC formation, growth and dissolution are discussed by means of kinetic lattice Monte Carlo simulations.

This paper presents charge trapping (CT) cells integrated with a sacrificial liner at the word line (WL) side wall which improves significantly the erase and retention characteristics, currently the main issues in CT memory devices.

Reactive ion etching using BCl3-based plasma chemistries is a promising technique to pattern high-k metal gate stacks. High-k materials for non-volatile memory and CMOS applications, in particular Al2O3, possess high chemical resistance. Accordingly, a steep sidewall angle at the device edges is difficult to achieve by reactive ion etching. Advanced etch conditions at elevated temperatures (above 250 °C) is an alternative to solve this challenge but generate various other technological difficulties. In particular the patterning of TANOS devices reveals severe etch damage effects at the metal gate layer. A study of damage protection has been carried out and in particular the chemical stability of different metal gate options during plasma treatments was investigated in detail. Advanced process approaches to prevent the metal gate deterioration are proposed.

In our work we present statistical methods and new memory array analysis approaches for decomposition and assessment of contributors to the Vth distribution widening. There, cell threshold voltage characteristics along bitlines and wordlines are considered as well as hidden systematic effects by convolutional analysis. Based on investigations on sub-50 nm floating gate NAND memory arrays we demonstrate an analysis method to distinguish between different reasons for broadened distributions by means of memory map analysis algorithms and filters. The impact of systematic threshold voltage and cell current variation in memory arrays caused by intrinsic circuit properties will be discussed.

In this work we present a systematic investigation concerning the correlation of Random Telegraph Noise (RTN) with erratic bits in sub-50nm floating gate NAND memory cells. Both effects are compared with respect to their implication in reliability and cell operation parameters of sub-50nm flash devices. Related measurements were performed on a test chip with large floating gate cell arrays in NAND architecture. The analysis methods for both effects are presented comparing the magnitude and cycling stress dependency in detail. Additionally, two integration concepts with different memory cell sidewall oxidation approaches are discussed effecting differently the RTN and erratic programming behavior. Based on the characterization results we conclude that both effects are originating from different trap mechanisms. Possible explanations for the different trap mechanisms and locations are discussed.

TANOS-NAND flash process integration generates various technological difficulties; one of the most relevant is the patterning of TaN metal gates together with Al2O3 high-k dielectrics. BCl3/N2 based high-temperature plasma etching preferably used for structuring high-k materials reveals severe etch damage effects at the TaN sidewalls. Plasma treatments with different etch gases (BCl3/N2; O2/Ar; Cl2/Ar) were used for detailed analyses of chemical effects on the TaN layer. The damage induced by BCl3/N2 based plasma was investigated and characterized using blanket wafers. Approaches to overcome this obstacle are proposed.

Au nanocrystals (NCs) were synthesized in a thin SiO2 layer by ion implantation and annealing in a tight distribution close to the Si/SiO2 interface. Between the NCs and the Si substrate a thin tunneling oxide forms self-organized during annealing totally depleted from Au NCs. Memory behavior is demonstrated by electron charging and discharging on metal–oxide–semiconductor capacitors. Lenticular liquid Au:Si droplets nucleate at the Si/SiO2 interface from silicon regions supersaturated by Au close to the oxide. Au NCs embedded in SiO2 above these droplets are stabilized during annealing due to a modified detailed balance of Au atom detachment and attachment. Capacitance-voltage and spreading resistance measurements reveal the impact of the Au contamination in the Si substrate. Structure and distribution of Au droplets and NCs are characterized by x-ray diffraction and transmission electron microscopy.

The elemental redistribution and Ge loss in low-energy ${\mathrm{Ge}}^{+}$ implanted ${\mathrm{SiO}}_{2}$ films during wet-chemical cleaning and annealing procedures are investigated. Two effects of major importance for Ge nanocrystal formation have been found. Moisture components (${\mathrm{H}}_{2}\mathrm{O}$ vapor, ${\mathrm{H}}^{+}$, ${\mathrm{OH}}^{\ensuremath{-}}$) penetrate into the damaged oxide during storage, wet chemical cleaning, or annealing procedures and lead to a hydrogen and oxygen enrichment in the near-surface oxide. Furthermore, atomic collisions during Ge implantation result in an oxygen excess (with respect to ${\mathrm{SiO}}_{2}$ stoichiometry) underneath the Ge profile. The local net ratio of Ge and excess oxygen determines, whether the implanted Ge is incorporated into the ${\mathrm{SiO}}_{2}$ network as spatially fixed ${\mathrm{GeO}}_{2}$, oxidizes to mobile $\mathrm{GeO}$, or remains as elemental Ge forming nanocrystals. Apart from very shallow profiles, where a drastic Ge loss is observed simply by cleaning in chemical solutions containing ${\mathrm{H}}_{2}{\mathrm{O}}_{2}$, the main Ge loss occurs during annealing. The highly mobile $\mathrm{GeO}$ is identified to be responsible for both, Ge redistribution or even loss, if diffusing $\mathrm{GeO}$ meets the ${\mathrm{SiO}}_{2}$ surface and emanates into the annealing ambient. Annealing in $\mathrm{Ar}∕{\mathrm{H}}_{2}$ mixtures at $\ensuremath{\le}900\phantom{\rule{0.2em}{0ex}}\ifmmode^\circ\else\textdegree\fi{}\mathrm{C}$ reduces the Ge loss due to the reduction of Ge oxides. The enhanced Ge mobility (as $\mathrm{GeO}$) is described as an oxygen vacancy assisted mechanism which also explains the influence of the $\mathrm{Si}∕{\mathrm{SiO}}_{2}$ interface on the Ge diffusivity. Finally, the consequences of Ge redistribution and loss for Ge nanocrystal memory device fabrication are discussed.

We have observed a very inhomogeneous dissociation of stoichiometric and non-stoichiometric thin SiO2 layers (thermally grown on Si substrates) during high temperature annealing at a low partial pressure of oxygen. During this process some silicon of the (100)Si substrate and, in case of Si ion implantation, and additionally, excess Si is consumed. The SiO2 dissociation has been studied by electron microscopy and Rutherford backscattering spectrometry. Large holes (>1 μm) in non-implanted oxide layers have been observed which evolve probably from defects located at the Si∕SiO2 interface. For Si implanted SiO2 additionally the formation of voids within the oxide during annealing has been observed preferably at the position of the implanted Si excess. Oxygen vacancies are possibly emitted from Si∕SiO2 interfaces into the oxide and migrate through SiO2 with long-range distortions of the oxide network. In that way the hole and void formation in the oxide can be explained by oxygen-vacancy formation, migration and silicon-monoxide (SiO) emanation. As a driving force for growth of the large holes we identified oxygen diffusion from the Si∕SiO2 interface to the bare Si surface. This surface is a sink of oxygen diffusion due to the emanation of volatile SiO, whereas the Si∕SiO2 interface serves as an oxygen source. The predicted mechanism is consistent with the geometry of the holes in the SiO2 layer.

Since the mid 90s the multidot memory has been of major interest in the research activities of emerging non-volatile memory devices [1, 2]. This memory concept is based on a layer of well separated Si or Ge nanocrystals (NCs) embedded in the transistor gate oxide substituting the floating gate of classical Flash-memory devices. Among various techniques for NCs fabrication [3] ion-beam synthesis (IBS) has been established as a versatile method to produce a high density (> 10 cm) of small (< 3 nm) Ge or Si NCs in thin gate oxides [4, 5]. Multidot memories likewise promise short programming / write times (tprog < 1 μs), low operating voltages (|Vprog| n 10 V) as well as high endurance (10 cycles) with preferably long data retention [1, 6, 7].

A Ge nanocrystal layer embedded in a thin gate oxide was prepared by ion beam synthesis in direct-tunneling distance to the Si substrate. The write performance was investigated in metal-oxide-semiconductor capacitors by means of capacitance measurements. With the experimental data and calculations using a floating-gate-like approach, the distribution of the tunneling oxide thickness dtox can be determined in high precision confirmed by high-angle annular dark-field scanning transmission electron microscopy imaging. The evolution of dtox during heat treatment is discussed in terms of Ostwald ripening; i.e., dtox increases with annealing time.

Three different approaches for the IBS of nanocrystals in the gate oxide of MOS structures were discussed. In all cases clear memory behaviour was observed. A variance of multidot devices from DRAM-like to non-volatile-semiconductormemory-like applications was shown. For high-dose IBS swelling, sputtering and IF-mixing have to be taken into account, which have a strong influence on the memory capabilities. It has been found that for Si-IBS or Ge-IBS, annealing influences the elemental depth profiles and the corresponding NC-distribution in a very different way. As a consequence, samples prepared by Si-IBS tend more to NVRAM-like behaviour, whereas the redistribution of Ge observed in Ge-LE-IBS provides DRAM-like properties. The latter combines the formation of NCs in a short distance to the Si substrate caused by IF-irradiation with a high density of small, well-separated NCs, which are fundamental requirements of common and future memory devices. Thus, IBS has the potential for use in cost-effective multidot memory applications, for example, in a multidot DRAM with prolonged retention time.

This paper describes a novel silicon detector with improved linearity characteristics for energetic electrons up to 50 keV. The modified pn-junction detector stracture contains a buried implanted n(+) layer (N ∼ 1-5 × 1015 cm-3) in the n-type Si substrate, which is attributed by a near-surface high-field region in the depletion zone. To enable a high-field region of several micrometers depth, high-energy ion implantation with 31p ions of 10-30 MeV was used. The corresponding electric field distribution of the novel detector is characterized by a constant electric field strength of 10-50 kV/cm from the surface down to the depth of the buried implanted layer. Detectors with considerable improved linearity up to electron current densities of 20 A/cm2 were been fabricated, which have been tested at the e-beam writer SB 350 of Leica Microsystems Lithography for electrons of 50 keV.

(Molecular absorption spectrometry with electrothermal vaporization in a graphite cuvette. Part 12. Determination of chloride species in selenium and AIIIBV-semiconductor materials after separation of the traces by adsorptive precipitation and distillation.) The determination of traces of chloride in chloride-dosed selenium and in gallium arsenide by molecular absorption spectrometry of AlCl is described. The traces of chloride are separated by adsorption precipitation (AgCl/Al2O3). The AgCl is dissolved in ammonia. After addition of Al3+ and Ba(OH)2 the molecular absorption of AlCl is measured at 261.4 nm. It is possible to determine 0.2 μg g−1 Cl in 500 mg of Se or GaAs.