Hardware design automation faces challenges in generating high-quality Verilog code efficiently. This paper introduces VFlow, an automated framework that optimizes agentic workflows for Verilog code generation. Unlike traditional approaches relying on fixed prompts or manually designed flows, VFlow treats workflow discovery as a search over graph-structured LLM invocation sequences. It introduces a multi-population cooperative evolution (CEPE-MCTS) algorithm that balances multiple hardware objectives – functional correctness, area, power, timing and token cost – while sharing successful patterns and avoiding repeated failures. Integrated multi-level verification ensures syntactic correctness, functional behavior, and synthesizability. Experiments on VerilogEval and RTLLM2.0 show VFlow improves pass@1 by 20–30% over prompting baselines and closely matches designer-level area/power. Remarkably, VFlow enables small LLMs to outperform larger models with up to 10.9× ROI, offering a cost-effective solution for RTL design. This work paves the way for intelligent, automated hardware development, advancing LLM applications in EDA.

Data-driven thermal predictors for 3D-ICs are often trained from scratch for each chip design using many high-fidelity finite-element simulations, leading to high data-generation cost and costly cross-design reuse. We propose Therm-FM, a neural operator framework that adapts a pretrained partial differential equation (PDE) foundation model to steady-state and transient 3D-IC thermal simulation. The motivation is that steady-state and transient chip-level heat conduction respectively share elliptic and parabolic operator structures with diffusion-type PDEs, allowing pretrained diffusion priors to provide an effective initialization for thermal-field prediction under heterogeneous materials, dense TSV/microbump interconnects, and package-level boundary conditions. To further reduce data-generation cost, Therm-FM incorporates a thermal-equivalent multi-fidelity training strategy that uses low-cost approximate simulations for thermal-domain adaptation and limited high-fidelity samples for calibration. Experiments on public HotSpot benchmarks and industrial 3D-IC package benchmarks show that Therm-FM achieves up to a 10.6x reduction in mean error and surpasses prior best accuracy with less than 20

Yield Multi-Corner Analysis validates circuits across 25+ Process-Voltage-Temperature corners, resulting in a combinatorial simulation cost of O(K × N) where K denotes corners and N exceeds 10^4 samples per corner. Existing methods face a fundamental trade-off: simple models achieve automation but fail on nonlinear circuits, while advanced AI models capture complex behaviors but require hours of hyperparameter tuning per design iteration, forming the Tuning Barrier. We break this barrier by replacing engineered priors (i.e., model specifications) with learned priors from a foundation model pre-trained on millions of regression tasks. This model performs in-context learning, instantly adapting to each circuit without tuning or retraining. Its attention mechanism automatically transfers knowledge across corners by identifying shared circuit physics between operating conditions. Combined with an automated feature selector (1152D to 48D), our method matches state-of-the-art accuracy (mean MREs as low as 0.11%) with zero tuning, reducing total validation cost by over 10×.

Power supply noise has emerged as a critical bottleneck in modern integrated circuit design, where increasing current densities and higher operating frequencies pose significant challenges to system reliability. While decoupling capacitors (decaps) serve as the primary solution for suppressing power delivery network (PDN) noise, determining their optimal values and placement remains computationally prohibitive using traditional methods. This article introduces ConvGA, a novel framework that seamlessly integrates convolutional neural networks (CNNs) with genetic algorithms (GAs) to revolutionize PDN decap optimization. At the heart of ConvGA is a specialized CNN architecture trained on comprehensive boundary element method (BEM) simulations, enabling ultrafast impedance prediction for arbitrary PCB configurations. Our CNN achieves remarkable accuracy while reducing impedance computation time from hours to mere milliseconds-a 500 & times; speedup over conventional BEM calculations. This acceleration enables the GA to efficiently explore vast design spaces through adaptive population control and dynamic constraint mechanisms, systematically minimizing both the number of required capacitors and the deviation from target impedance. Extensive experiments on industrial-scale PDNs demonstrate that ConvGA achieves a 15 & times; reduction in optimization time while requiring 30% fewer capacitors compared to state-of-the-art methods, consistently producing high-quality solutions across diverse PDN configurations.

With the advancement of modern nanoscale technology nodes, static timing analysis (STA) has become an indispensable technique for ensuring circuit reliability and performance across diverse process conditions. However, traditional STA methods scale poorly to the explosion of process corners in the nanoscale fabrication technology. Despite some seminal works in using AI to accelerate such processes, they either lack reliability or stability. To this end, we introduce active self-attention neural process (ASAP), a novel approach addressing this challenge by combining both the latest deep learning methods and the classical Bayesian models to deliver scalable and accurate predictions with a self-calibration strategy to ensure reliability. Technically, the ASAP novelly integrates self-attention to help identify and prioritize crucial features under various input conditions and employs neural process to make confidence-based predictions for the final timing results. Furthermore, ASAP is equipped with Active Learning for self-refinement and self-correction. Experimental evaluations on benchmark circuits demonstrate that our method surpasses state-of-the-art work in STA accuracy by 18% in terms of prediction accuracy.

Advanced packaging with chiplet heterogeneous integration represents a critical “More than Moore” approach, but thermal simulation faces a fundamental bottleneck: the dramatic scale disparity between system components (mm-scale) and thermal-critical micro-structures like TSVs, μbumps, and RDLs (μm-scale). Existing methods force an impossible trade-off between computational tractability and micro-scale accuracy, constraining thermal-aware design optimization in next-generation heterogeneous systems. We present H2-Thermal, a paradigm-shifting framework that abandons uniform discretization in favor of adaptive hierarchical modeling that mirrors the physical chiplet construction. Our key insight is leveraging the natural layer-wise architecture of heterogeneous integration to enable cross-scale thermal simulation without global mesh alignment constraints. The framework combines adaptive-enveloping mesh generation for micro-structures, virtual meshing for accurate thermal resistance extraction across misaligned interfaces, and physics-informed model order reduction that preserves critical thermal pathways while eliminating computational redundancy. Evaluated on industrial-grade benchmarks spanning 2.5D and 3D packaging architectures, H2-Thermal achieves 28.61× speedup and 4.37× memory reduction compared to state-of-the-art commercial simulators while maintaining temperature accuracy within 0.179%. More significantly, our approach enables a new class of thermal-aware design optimizations previously computationally intractable, resolving hotspot analysis for microscale interconnections within system-level contexts.

Importance sampling for high-sigma yield estimation requires locating the failure center from a severely imbalanced sample set. Existing surrogate-assisted methods rely on iterative gradient-based training, ill-posed under extreme class imbalance; model errors propagate into the estimator, causing accuracy collapse in high dimensions. We recast failure-center localization as few-shot binary classification: a prior-fitted tabular foundation model performs gradient-free in-context inference in a single forward pass, eliminating the ill-posed training loop. \textbf{HOLMES} (High-sigma Optimal Localization via Manifold Estimation and Sampling) pairs this with an SVD-based anisotropic proposal that captures the local geometry of the failure manifold, and a hit-rate-driven adaptive mixing scheme that stabilizes importance weights where conventional adaptation collapses. On 6T SRAM benchmarks spanning $D = 108$ to $D = 1{,}152$, full-dimensional baselines exhibit accuracy collapse at some dimension, with the strongest baseline reaching 25.8\% relative error; PCA+MNIS is additionally evaluated at the two largest dimensions. HOLMES remains within 5.9\% across all five configurations with up to $58.8\times$ speedup over Monte Carlo. The code is available on \href{https://github.com/IceLab-JCIE/ICE006-Yield-Holmes}

Traditional yield analysis for analog and mixed-signal (AMS) circuits relies heavily on Monte Carlo (MC) methods, which suffer from a fundamental information inefficiency: they reduce rich, continuous circuit performance metrics to binary pass/fail indicators. As process variations scale into high-dimensional spaces with advanced technology nodes, this inefficiency creates an insurmountable computational barrier. This paper proposes a Continuous Bayesian Inference framework that fundamentally transforms circuit yield analysis from discrete counting to probabilistic integration over the performance landscape. We introduce a Sparse Gaussian Process (SGP) model augmented with Deep Kernel Learning (DKL) to effectively capture the non-stationary correlations in high-dimensional variation spaces, reducing the computational complexity from O(n3) to O(nm2). Furthermore, we propose an information-theoretic active learning strategy based on convolutional entropy, which exploits the smoothness of circuit performance to optimally select samples that maximize uncertainty reduction. Experimental validation on benchmark circuits, including a 569-dimensional SRAM column, demonstrates that the proposed framework achieves a 34.30×-320.14× end-to-end speedup over standard MC. Furthermore, compared to state-of-the-art yield analysis baselines, it demonstrates 1.0×–5.24× end-to-end speedup. Additionally, SBYA can be seamlessly extended to yield optimization tasks, delivering comparable or even superior optimization efficacy while consuming merely one-quarter of the simulation budget required by existing methodologies.

We introduce Mixture-of-Trees (MoT), a novel framework that integrates sparse expert activation with structured tree-based reasoning for efficient LLM inference. MoT employs a learned gating mechanism to selectively activate only the most relevant expert reasoning trees for each problem, where experts use models of varying capacities based on task complexity. The framework features three key innovations: (1) sparse expert activation through unified gating networks, (2) specialized expert trees that leverage domain-specific expertise while optimizing the quality-efficiency trade-off, and (3) collaborative debate mechanisms for conflicting solutions. Additionally, MoT includes a shared baseline tree with early stopping—activated experts perform lightweight validation and terminate early when confidence is high. Experiments across five benchmarks (GSM8K, MATH, AIME 2024, MMLU, HotpotQA) show that MoT achieves 2-7 percentage point accuracy improvements while reducing LLM calls by 37-40% compared to existing multi-path methods.

Integrated circuit yield optimization plays a vital role in ensuring reliable semiconductor manufacturing, directly impacting both product quality and production costs. Current approaches to yield optimization face two fundamental challenges that limit their practical effectiveness. First, yield estimation requires intensive computational resources. Second, traditional black-box optimization methods inefficiently allocate these resources across design candidates. Most existing approaches compound these issues by performing detailed yield estimations uniformly across all candidates, regardless of their potential quality. To address these limitations, we introduce a novel precision-aware yield optimization framework that intelligently adapts computational resource allocation based on each design candidate's predicted performance. Our approach moves beyond simple simulation counting by incorporating a Figure of Merit (FoM) as a continuous quality metric. By combining a Continuous AutoRegression model to characterize the relationship between true yield and precision levels with a sophisticated multi-fidelity acquisition strategy, our framework achieves optimal resource distribution. Experimental validation on four industry-standard benchmark circuits demonstrates that our method converges with fewer than 1,000 simulations, reducing simulation costs by over 10x while achieving better final designs and robustness than state-of-the-art high-fidelity approaches.

Advancing technology nodes have significantly increased the complexity of transistor sizing in analog circuit design. Although artificial intelligence (AI) techniques show potential, their lack of integrated domain expertise often leads to slow convergence in practical applications. We propose ASTRA (Automatic Sizing of Transistors with Reasoning Agents), a novel optimization framework that implements the Model Context Protocol (MCP) to create structured reasoning pathways between Large Language Models (LLMs), domain knowledge bases, and Bayesian Optimization (BO). ASTRA introduces a two-stage process: first, MCP-guided design initialization that leverages Retrieval-Augmented Generation (RAG) to quickly identify feasible regions using gm/ID methodology; and second, BO-based optimization focused on critical transistors, identified through LLM reasoning with data-driven validation. A key innovation of ASTRA is its ability to seamlessly integrate with and enhance virtually any existing transistor sizing algorithm at minimal additional cost. Unlike purely data-driven or black-box LLM approaches, ASTRA maintains traceable decision processes that can be verified and refined. Evaluated on three real-world analog circuits, ASTRA enhances multiple classical optimization methods, achieving up to 4.35× fewer simulation iterations and 2.36× performance improvements, demonstrating its effectiveness as a general open-source framework for advancing analog circuit sizing. 1

In the post-Moore era, three-dimensional integrated circuit (3D-IC) technology is a key direction for continuing to enhance chip performance. However, in the thermal simulation field, existing works either only address two-dimensional temperature fields or require a large number of samples and a long training time to train the model. In order to meet the current demand in chip design for rapid and accurate thermal prediction with limited sample sizes, this paper introduces a multi-fidelity model, T-Fusion, which combines tensor arithmetic and Bayesian autoregression. Leveraging a sparse set of high-fidelity data alongside abundant low-fidelity samples, T-Fusion reliably estimates high-fidelity thermal distribution across the chip. We validate our model on single-core double-layer chips, quad-core triple-layer, and octa-core double-layer chips respectively. We compare the predicted heat distribution with commercial thermal simulation software such as COMSOL, MTA, and Hotspot, achieving accelerations of 10,000x to 1,000,000x. T-fusion can also be applied to transient temperature prediction of the chip, requiring only 20 sets of high-precision data and 64 sets of low-precision data to control ME under 1K.

Semiconductor yield estimation presents a critical challenge in modern manufacturing, directly impacting production costs and market competitiveness. Traditional estimation methods, particularly Monte Carlo simulation, while reliable, become computationally prohibitive for complex modern circuits. Contemporary approaches, including importance sampling and machine learning techniques, face fundamental limitations in consistency across circuit topologies and practical validation. This work introduces YieldAgent, a novel Large Language Model (LLM)-powered framework that revolutionizes yield estimation through dynamic integration of multiple analytical strategies. YieldAgent employs a three-layer agent architecture to analyze circuit characteristics and historical data, optimizing estimation methods while balancing computational efficiency and precision. The framework incorporates Retrieval-Augmented Generation for domain knowledge integration and Tree-structured Parzen Estimators for dynamic hyperparameter optimization. Experimental validation across 12nm and 40nm technology nodes demonstrates that YieldAgent reduces computational overhead by up to 2.9x while maintaining or exceeding state-of-the-art accuracy. The system's ability to adapt across different circuit topologies and technology nodes establishes a new paradigm for scalable, intelligent yield estimation in electronic design automation.

The design and high-throughput screening of materials using machine-learning assisted quantum-mechanical simulations typically requires the existence of a very large data set, often generated from simulations at a high level of theory or fidelity. A single simulation at high fidelity can take on the order of days for a complex molecule. Thus, although machine learning surrogate simulations seem promising at first glance, generation of the training data can defeat the original purpose. For this reason, the use of machine learning to screen or design materials remains elusive for many important applications. In this paper we introduce a new multi-fidelity approach based on a dual graph embedding to extract features that are placed inside a nonlinear multi-step autoregressive model. Experiments on five benchmark problems, with 14 different quantities and 27 different levels of theory, demonstrate the generalizability and high accuracy of the approach. It typically requires a few 10s to a few 1000’s of high-fidelity training points, which is several orders of magnitude lower than direct ML methods, and can be up to two orders of magnitude lower than other multi-fidelity methods. Furthermore, we develop a new benchmark data set for 860 benzoquinone molecules with up to 14 atoms, containing energy, HOMO, LUMO and dipole moment values at four levels of theory, up to coupled cluster with singles and doubles.

CMOS scaling faces challenges due to lithography and device physics issues, leading to increased costs and difficulties in expanding chip footprint. 3D integration technology offers increased integration density without increasing footprint, but elevated power density makes heat dissipation a significant challenge. Microchannel cooling effectively removes heat inside 3D chips. Traditional microchannel optimizations typically focus only on minimizing pump power within a limited parameter design space, leading to suboptimal cooling efficiency. Moreover, existing research rarely considers manufacturing costs, limiting practical application. To address these issues, we propose a high-dimensional non-uniform microchannel design scheme based on Segmented Sampling Bayesian Optimization (SSBO). This multi-parameter collaborative optimization framework comprehensively optimizes microchannel design. Our method reduces pump power by 70% compared to limited parameter design spaces. Additionally, we introduce a cost model for microchannel design, formulating a multi-objective optimization problem that considers both manufacturing cost and pump power consumption. By solving the multi-objective optimization problem by searching for the Pareto front, we demonstrate a balanced design between microchannel manufacturing cost and pump power and provide guidelines for key design parameters.

Large language models (LLMs) have transformed code generation, yet their application in hardware design produces gate counts 38%–1075% higher than human designs. We present CircuitMind, a multi-agent framework that achieves human-competitive efficiency through three key innovations: syntax locking (constraining generation to basic logic gates), retrieval-augmented generation (enabling knowledge-driven design), and dual-reward optimization (balancing correctness with efficiency). To evaluate our approach, we introduce TC-Bench, the first gate-level benchmark harnessing collective intelligence from the TuringComplete ecosystem – a competitive circuit design platform with hundreds of thousands of players. Experiments show CircuitMind enables 55.6% of model implementations to match or exceed top-tier human experts in composite efficiency metrics. Most remarkably, our framework elevates the 14B Phi-4 model to outperform both GPT-4o mini and Gemini 2.0 Flash, achieving efficiency comparable to the top 25% of human experts without requiring specialized training. These innovations establish a new paradigm for hardware optimization where collaborative AI systems leverage collective human expertise to achieve optimal circuit designs. Our model, data, and code are open-source at https://github.com/BUAA-CLab/CircuitMind.

Analog in-memory computing (IMC) promises unprecedented energy efficiency for deep learning acceleration, but suffers from non-idealities that severely degrade inference accuracy in fabricated chips. Therefore, accurate modeling of these non-idealities becomes significant. In this work, we present PDGM-IMC, the first physics and data co-driven generative framework for IMC non-idealities characterizing. Unlike traditional physical models that fail to model complex non-ideality behaviors, or black-box neural networks that lack interpretability and generalization, PDGM-IMC leverages normalizing flows with custom transformations directly derived from device physics principles. This novel approach enables explicit modeling of complex probability distributions, spatial correlations, and die-to-die variations that previous methods could not capture. Validated on multiple dies of a commercial eFlash-based IMC SoC, PDGM-IMC improves modeling accuracy by 4.6× for the input circuit and IMC array and by 2.0× for the output circuit, significantly outperforming existing approaches. By extracting the statistical signature of fabricated chips, PDGM-IMC enables accurate pre-silicon prediction of post-silicon behavior, fundamentally transforming hardware-aware neural network optimization for analog accelerators. The source code and the pre-trained models are publicly available at https://github.com/BUAA-BASIC-Lab/PDGM-IMC.

As Cu interconnects near their physical limits with continued technology scaling, carbon nanotube (CNT) interconnects have emerged as a promising alternative due to their excellent conductivity. However, fabrication immaturity introduces significant process variations, causing discrepancies between ideal and actual performance. This article presents a novel approach to optimize CNT interconnects considering process variations. We first develop a parameterized CNT interconnect model that accounts for process variations. Using this model, a Bayesian neural network (BNN) is proposed to predict performance distributions by leveraging its inherent uncertainty. We then introduce a Bayesian optimization framework that uses the BNN's posterior to jointly optimize interconnect parameters and buffer insertion, targeting area-delay product (ADP) with process variations. Experimental results demonstrate the effectiveness of our approach. The proposed BNN model achieves over 95% prediction accuracy for interconnects performance distributions. Compared to existing methods, our method achieves an average ADP improvement of 20.3% over the state-of-the-art methods and 13% over the standard Monte Carlo method. Compared with Monte Carlo method, our method also achieves an average $8.8\times $ acceleration. Moreover, the optimized CNT interconnects show an average improvement of 82.8% in ADP and 68.7% in delay compared to Cu interconnects. This work offers an effective method for optimizing CNT interconnects under process variations and highlights their potential as a viable alternative to Cu interconnects in future integrated circuits.

Static Random-Access Memory (SRAM) yield analysis is essential for semiconductor innovation, yet research progress faces a critical challenge: the large gap between simplified academic models and the complexities observed in practice. The lack of open, higher-fidelity benchmarks has hindered reproducibility and transferability, as promising academic techniques often fail to carry over to more realistic settings. We present OpenYield, an open-source ecosystem that aims to narrow this gap through three contributions: (i) An SRAM circuit generator that explicitly incorporates second-order effects (interconnect/line parasitics, inter-cell leakage coupling, and peripheralcircuit variations) that are commonly omitted in academic studies. (ii) A standardized evaluation platform with a simple interface and baseline yield-analysis implementations to enable fair comparisons and reproducible research on these higherfidelity circuits. (iii) An optimization platform for transistor-level sizing under these models, supporting reproducible studies of robustness/efficiency trade-offs. OpenYield aims to foster more reproducible and transferable progress in SRAM-yield research. The framework is publicly available at OpenYield:URL.

Device models require large numbers of parameters to characterize complex physical effects. Although the latest advancements in machine learning and automated tools have drastically improved efficiency over the classic methods, they still demand a considerable amount of human intervention in the loop to gain accuracy. This drastically limits further automation. Inspired by the success of Multimodal Large Language Models (MLLMs) in addressing tasks across diverse fields, we propose ModelGen, the first in-depth study to leverage MLLMs with RAG (Retrieval-Augmented Generation) to significantly reduce human effort in parameter extraction for compact model. Our contributions include (1) Automated Agentic Workflow Construction that learns to build and refine extraction workflows through iterative optimization, (2) MLLM Judge, a visual scoring mechanism that evaluates fitting quality using actual device characteristic plots rather than simple numerical metrics, and (3) Model-specific RAG for providing relevant domain knowledge during the extraction process. Experimental results demonstrate that ModelGen achieves a 26.8%-33.1% improvement in pass@1,3,5 compared to base LLM methods. The system completes complex model extractions for BSIMs and ASM-HEMT in hours (up to 168x faster) rather than days or weeks, making parameter extraction more accessible to non-experts while maintaining professional engineer-level accuracy.