Three-dimensional complementary metal-oxide-semiconductor technology integrating carbon nanotubes and silicon presents a promising pathway for the fabrication of beyond-Moore integrated circuits. Herein, we present an ionizing-irradiation-involved integration process towards ultra-low-power fabrication, completely compatible with the 3D integration process. As the fundamental building blocks of digital circuits, inverter cells are examined to verify the effectiveness of this proposed methodology. Furthermore, comparative experiments combined with numerical simulations are utilized to thoroughly investigate transistor-level radiation effects, revealing the governing mechanisms of power reduction. By incorporating Cobalt-60 u03B3-ray irradiation within the wafer-scale 180-nm-node 3D integration, the threshold voltage mismatch between p-type and n-type transistors can be resolved without significant modifications to the process flow. With optimized ionizing radiation doses and bias conditions, the switching threshold voltages of the 3D CMOS inverters improves from 0.400u00D7 to 0.495u00D7 of the supply voltage VDD (a 24.2% improvement), closely approaching the ideal value of 0.5u00D7 VDD. This optimization leads to a distinct increase in the noise margin low from 0.276u00D7 to 0.373u00D7 VDD (a 35.1% enhancement), significantly boosting the reliability of the digital circuit cells. More importantly, the minimal operational VDD of the inverters is remarkably reduced from 0.5 to 0.2 V. An ultra-low minimal peak dynamic power of 8.33 pW (831u00D7 reduction by the ionizing irradiation) is achieved, which is amongst the lowest values in publications.

In this article, the electrostatic discharge (ESD) performance of gate‐structure‐defined diodes (gated diodes) based on stacked SiGe/Si fin field‐effect transistor (FinFET), Si channel gate‐all‐around field‐effect transistor (GAA), and SiGe channel GAA structure in GAA technology is investigated in detail by using 3D TCAD simulations. The stacked SiGe/Si FinFET demonstrates superior ESD robustness, exhibiting a significantly higher failure current (I t2 ) and the lowest on‐resistance ( R on ) among the tested structures. Meanwhile, the transmission line pulse (TLP) current conduction and failure mechanism in these gated diodes are examined through physical analysis. The results reveal that current crowding leads to early thermal failure and I t2 deterioration. Additionally, the I t2 of stacked SiGe/Si FinFET can be further improved by 6% as the Si and SiGe thickness ratios are optimized from 6/12 to 12/6 nm. These findings suggest that the optimized stacked SiGe/Si FinFET gated diode is a promising candidate for ESD protection in GAA technology.

This work introduces a novel post-fabrication electromagnetic pulse (EMP) injection technique for optimizing the on-resistance-breakdown voltage (R-ON-BV) trade-off in bulk lateral double-diffused MOSFETs. Experimental results demonstrate significantly higher BV modulation efficiency in devices with thick gate oxides compared to thin gate oxide counterparts with unchanged on-resistance (R ${}_{\text {ON}}\text {)}$ . This comparative analysis combined with AI-assisted TCAD simulations conclusively identifies the unique distribution of trapped charges within the gate oxide as the dominant mechanism responsible for BV shift. These findings demonstrate that the post-process EMP-induced BV enhancement without typical degradation in R-ON provides a new approach for overcoming the fundamental R-ON-BV trade-off in power semiconductors.

Abstract This study examines the electrostatic discharge (ESD) reliability of local-bottom-gate carbon nanotube (CNT) field-effect transistors (FETs) fabricated with randomly distributed networks. Transmission line pulsing (TLP) and very-fast TLP (VFTLP) techniques have been used for characterization. The devices show bidirectional ESD responses governed by distinct conduction mechanisms. Transient waveform analysis combined with scanning electron microscopy (SEM)/transmission electron microscopy (TEM) imaging reveals that thermal effects dominate the breakdown process. The maximum destructive second failure current reaches 0.25 mA/µm under the human body model conditions and 0.8 mA/µm under the charged device model conditions. This work establishes a quantitative benchmark for the ESD performance of CNT FETs, clarifies the intrinsic failure mechanisms, and demonstrates that structural modifications can improve robustness. These findings provide guidance for the design of CNT-based devices with improved reliability and lay the groundwork for their integration into future electronic systems.

3D integration presents a potential technical solution to break the fundamental transistor density limit of the ground rule scaling. Despite notable progress, the unavoidable high thermal budget in conventional silicon‐transistor‐based 3D integration results in high process complexity and degraded device performances. Herein, a heterogeneous 3D complementary metal‐oxide‐semiconductor field effect transistor (CMOS FET) technology, integrating carbon nanotube (CNT) transistors into Si back‐end‐of‐line (BEOL) processes is presented. Experiments show that CNT transistors can be integrated using a low‐thermal‐budget (<150 °C) process, requesting little modification in the well‐established Si processes. Comparative analysis also indicates that the low‐thermal‐budget integration results in little damage to the Si components. More importantly, Si‐BEOL‐compatible gate control enhancement and threshold voltage modulation techniques for CNT transistors are developed, resulting in noise margin improvement and power suppression in inverters. The experimental results further demonstrate that CMOS FET inverters feature high noise margins ( NM H / NM L = 0.404/0.353 × V DD ) and ultra‐low power consumption (390 pW, >100× lower than those in the Si counterparts). Moreover, numerical simulations predict that 14‐nm‐node CNT/FinFET 3D CMOS FET inverters outperform the conventional FinFET counterparts in noise margins and power efficiency. These findings demonstrate the possibility of 3D integration's complexity reduction by adopting <150 °C CNT‐based processes.

The total-ionizing-dose (TID) effect in p-type top-gate carbon nanotube field-effect transistor (CNT FET) under ON, OFF, transmission gate (TG), and All-0 bias conditions is investigated through experiments and simulations. The continuous application of electrical stress incites degradation in the device characteristics of CNT FETs, which is further complicated by the superimposition of TID effects. This work distinguished between the electrical stress impact and the TID effect through comparative experiments and analyzed the underlying mechanisms of these two effects with technology computer-aided design (TCAD) simulations. The experimental results demonstrate that both effects on CNT FETs mainly result in a threshold voltage shift. Electrical stress results in a Delta V-th of -0.1 V (OFF state) to +0.2 V (ON state), while the TID effect results in a Delta V-th of -0.15 V (TG state) to -0.05 V (ON and OFF states). The TG state is recognized as the worst case bias condition of the TID effect on CNT FETs. TCAD simulation results denote that electrical stress incites changes in the trap charge density (similar to 10(12) cm(-2)) in the gate dielectric layer, while the TID effect augments positive fixed charges (similar to 10(11)-10(12) cm(-2)) in the substrate oxide. This study explains the mechanisms of electrical stress and TID effects in CNT FETs, providing a reference for subsequent device process optimization and radiation hardening.

Seawater electrolysis is considered a promising technology to realize large scale hydrogen production due to the sufficient seawater resources, but facing challenges in catalysts activity and efficiency. Herein, we propose a strategy to modulate the electronic structure of bimetal nitrides via simultaneously introducing metallic Ni and N vacancy (Ni/(Ni,Co)3Nv), enabling the highly efficient and stable hydrogen generation in alkaline seawater was achieved. The catalyst exhibits low overpotentials of only 185 mV and 297 mV at 100 mA cm- 2 and a large current density of 1000 mA cm- 2 for hydrogen evolution reaction (HER) in alkaline seawater, respectively. The theoretical calculations reveal that the metallic Ni and N vacancies can synergistically optimize the d band center and charge distribution, thus accelerating water dissociation kinetics and optimizing H adsorption energy. Notably, the assembled AEM electrolyzer by coupling Ni/(Ni,Co)3Nv||NiFeLDH-Ni/(Ni,Co)3Nv exhibits outstanding stability over 100 h at 500 mA cm- 2 in alkaline seawater.

A novel silicon-controlled rectifier (SCR) device is proposed to achieve adjustable holding voltage (V-h) and strong radiation tolerance. The proposed SCR devices are fabricated in 0.18-mu m silicon-on-insulator (SOI) technology by inserting the very shallow trench isolation (VSTI) with different lengths in the n-well between the anode region and polysilicon. The adjustable V-h ranging from 2.0 to 4.8 V is achieved by changing the length of VSTI from 0.3 to 3 mu m. The influence of total ionizing dose (TID) on VSTI-SCR devices is investigated by experiments and simulations, and strong radiation tolerance up to 500 krad(Si) is proved for the VSTI-SCRs. It is concluded that its triggering voltage decreases by about 19%-31% with the radiation dose increase from 0 to 500 krad(Si), which is beneficial for the operation of VSTI-SCR devices. V-h decreases by approximately 15%, which is overlapped by the ESD-design window of 1.2x V-DD-0.8x V-BD. Whereas, as the length of VSTI increases, V-h elevates and the effect of TID on V-h of SCR devices remains almost unchanged, which means that the latch-up risk of VSTI-SCR induced by TID could be eliminated by broadening VSTI length properly.

With the scaling down of feature sizes, the single-event multiple transient (SEMT) effect becomes increasingly significant. This paper proposes a novel SEMT modeling approach based on artificial neural network (ANN). The method can accurately captures the relationship between device placement pitch, linear energy transfer, drain voltage, time and transient current without consideration of sophisticated physical mechanisms unsuitable for circuit-level simulation. Two ANN models are developed for active and passive devices in 28nm bulk technology, respectively. The models achieve root-mean-square errors of 2.99 × 10−4 and 1.34 × 10−2, demonstrating high accuracy in characterizing the multi-transient pulses caused by single-particle strikes. These models are implemented as fault injection sources using Verilog-A language, with their practicality validated through SPICE simulation of a two-stage inverter chain. Simulation results reveal that due to the SEMT, the output pulse width of the inverter chain exhibits pulse quenching effect.

The electrostatic discharge (ESD) and failure mechanisms of carbon nanotube field-effect transistors (CNT FETs) were thoroughly investigated via transient current tests and numerical simulations. Experiments demonstrated that CNT FETs have a three-stage ESD process according to transmission-line pulse (TLP) and human-body model (HBM) measurements, vastly different from the snapback phenomenon in conventional Si CMOS transistors. As the drain bias (VDS) increases from 2 to 12 V, the ESD mechanism of CNT FETs changes from thermionic emission (first stage) to band-to-band tunneling (second stage), which results in a dynamic discharge impedance. The soft breakdown of the drain-to-gate isolation dielectric contributes to the discharge current in the third stage when VDS > 12 V. The breakdown current-induced heating of CNT FETs can cause critical damage to the drain-to-gate isolation dielectric and the metal contacts and eventually result in device failure. Therefore, the drain-to-gate isolation dielectric is identified as the weak spot, requiring optimization to enhance the reliability of CNT FETs.

Protecting integrated circuits against electrostatic discharge (ESD) remains a persistent challenge within the semiconductor industry, garnering significant attention from the research and industrial sectors. To effectively discharge substantial ESD current away from sensitive devices, on-chip ESD protection is required to become conductive within mere nanoseconds and then return to an insulated state after the event. Insulator-metal transition (IMT) materials intrinsically possess this property. Little research has been done on the electrostatic discharge characteristics of the well-known IMT material Niobium oxide (NbO2). In this study, we execute transmission line pulse (TLP) assessments on 50-nm NbOx vertical construct and analyze ESD characteristics and failure mechanisms utilizing X-ray photoelectron spectroscopy, scanning electron microscopy, etc. The snapback behavior is observed in the device’s TLP I-V curve. The results show the promise of IMT materials for on-chip ESD/EOS protection.

The impact of the total ionizing dose (TID) on low leakage electrostatic discharge (ESD) protection devices fabricated on the 180-nm double silicon on insulator (DSOI) technology is investigated through experiments and numerical simulations. The devices under tests (DUTs) are MOS-DIO, MOS-SCR, and gate-grounded NMOSFET (GGNMOS). The transmission line pulse (TLP) measurements were carried out before and right after Co-60 gamma ray irradiation. The results show that the radiation-induced charges and traps mainly located in the top buried oxide (BOX1) can lead to deterioration of ESD characteristics, such as leakage and triggering voltage. After being irradiated to a dose of 300 krad(Si), the leakage of GGNMOS increases by about three orders of magnitude, and in addition, its snapback characteristic vanishes. Radiation hardness on DSOI-based ESD devices is analyzed based on experiment and simulation results, which implies that the negative voltage on back-gate electrode can mitigate the deterioration of ESD characteristics caused due to irradiation.

A novel implementation for electrostatic discharge (ESD) protection is demonstrated, which involves two structures named MOSFET in parallel with diode (MOS-DIO) and MOSFET in parallel with silicon-controlled rectifier (MOS-SCR). The fabricated structures exhibit enhanced robustness enabled through the double silicon-on-insulator (DSOI) technology. The implementation combines a MOSFET in the top silicon film with a diode or a silicon-controlled rectifier (SCR) located in the middle silicon layer. Transmission line pulse (TLP) experiments show that compared with the traditional single nMOS structure, both DSOI MOS-DIO and MOS-SCR exhibit superior current discharge capability with an increase in failure current of up to 39% under the same footprint. The leakage of the proposed structures is also reduced to below 0.2 pA/mu m thanks to the double buried oxide isolation. In addition, both triggering and holding voltages can be flexibly tuned via the positioning of the two shunt devices. Technology computer-aided design (TCAD) simulations were carried out for MOS-SCR to interpret the physical mechanism and predict the performance under different device parameters, including gate length, stacked modes, and ambient temperature.

Diodes based on p-n junctions are fundamental building blocks for numerous circuits, including rectifiers, photovoltaic cells, light-emitting diodes (LEDs), and photodetectors. However, conventional doping techniques to form p- or n-type semiconductors introduce impurities that lead to Coulomb scattering. When it comes to low-dimensional materials, controllable and stable doping is challenging due to the feature of atomic thickness. Here, by selectively depositing dielectric layers of Y2O3 and AlN, direct formation of wafer-scale carbon-nanotube (CNT) diodes are demonstrated with high yield and spatial controllability. It is found that the oxygen interstitials in Y2O3, and the oxygen vacancy together with Al-Al bond in AlN/Y2O3 electrostatically modulate the intrinsic CNTs channel, which leads to p- and n-type conductance, respectively. These CNTs diodes exhibit a high rectification ratio (>104) and gate-tunable rectification behavior. Based on these results, we demonstrate the applicability of the diodes in electrostatic discharge (ESD) protection and photodetection. [GRAPHICS]

In this article, high-voltage (HV) electrostatic discharge (ESD) protection devices with high robustness and strong radiation tolerance are investigated by technology computer-aided design (TCAD) simulations and transmission line pulse (TLP) measurements. The TLP measurement results of laterally diffused MOS (LDMOS)-silicon-controlled rectifier (SCR) fabricated in 0.35 mu m bipolar-CMOS-DMOS (BCD) process demonstrated that its ESD robustness is elevated by 58% than that of LDMOS and is up to 13 kV human body model protection level. Meanwhile, high holding voltage and current of 17 V and 1.8 A are achieved by low-voltage MOS (LV-MOS) cascade technology in LDMOS-SCR. TLP I-V curves and transient voltage waveforms exhibit high operational stability of LDMOS-SCR. Gamma-ray irradiation experiments show strong radiation tolerance of LDMOS-SCR, whose ESD performance had almost no degradation under total ionizing dose (TID) radiation of 200 krad(Si), while the failure current of LDMOS decreased by 2 A. Therefore, a properly designed LDMOS-SCR is an excellent ESD protection device for HV circuits, especially in space applications.

The total ionizing dose (TID) effect of low operation voltage MOSFET (LV-MOS), medium operation voltage lateral double-diffused metal–oxide–semiconductor field-effect transistor (MOSFET) (MV-LDMOS), and 600-V high operation voltage LDMOS (HV-LDMOS) manufactured by silicon-on-insulator (SOI) bipolar-complementary metal–oxide–semiconductor DMOS (BCD) process is investigated by experiments and 3-D TCAD numerical simulations, and the hardening technique is proposed and discussed. The experiment and simulation results of LV-MOS with three different structures indicate that the TID-induced leakage current is mainly caused by the STI oxide, which forms a leakage current path along the side of the channel region. The leakage current of LV-MOS with a square/ring shape gate (RG-MOS) structure does not increase even though the irradiation dose increases to 300 krad(Si). The RG-MOS structure can eliminate the TID-induced leakage current induced by segregating the channel from the STI region, which is used in MV-LDMOS and 600-V HV-LDMOS. The TID-induced leakage current of radiation-hardened MV-LDMOS does not increase at the irradiation dose of 300 krad(Si). The TID-induced leakage current of radiation-hardened 600-V HV-LDMOS is about four orders of magnitude less than that of standard 600-V HV-LDMOS at the irradiation dose of 50 krad(Si). The specific-on-resistance performance of MV-LDMOS and 600-V HV-LDMOS is improved with the increase of irradiation dose. The radiation-hardened technique used in this article can improve the TID tolerance of MOSFETs in SOI BCD process significantly. The systematic and thorough investigation of TID hardening technique of SOI BCD technology will contribute to the application of power ICs in the space environment.

The electrical performance of high-precision analog and digital circuits in MOSFETs is highly sensitive to temperature changes. Here, by studying the stability of electrical characteristics such as OFF-state leakage current, saturation current, and transconductance efficiency of fully depleted silicon-on-insulator (FDSOI) and partially depleted silicon-on-insulator (PDSOI) in the temperature range of 25 °C–300 °C, we proposed a new semiconductor-parameter-temperature-increment (SPTI) model. Within this SPTI model, it can clarify the influence of high-temperature electrical parameters, $\alpha _{T}$ and $\beta _{T}$ , on the stability of the electrical characteristics of FDSOI and PDSOI. Thus, it helps in understanding the differences in the stability of electrical characteristics between the two devices. In addition, the SPTI model can also be used to obtain the design domain of the electrical characteristics for FDSOI and PDSOI. More importantly, a compromise method based on the design parameter $\gamma $ can be obtained to effectively improve the electrical characteristics and the stability of the two devices.

Partially-depleted silicon-on-insulator (PDSOI) MOSFETs with full dielectric isolation structure are widely used in the high temperature field of 225 °C, but affected by the threshold voltage and carrier mobility, the saturated output current has a rate of change as high as 24.9% at 25 °C–300 °C, which will reduce the working speed and accuracy of the analog circuit. This paper studies the high temperature output current characteristics of ultra-thin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) MOSFETs with the 28 nm low voltage threshold structure. The experimental results show that when the gate voltage of the device is constant, the saturation current change of 28 nm short-channel FDSOI device is 1.93% in the temperature range from 25 °C to 300 °C, which is 12.9 times more stable than that of 0.13 μm PDSOI device, 4.5 times and 8.4 times higher than that of 0.3 μm and 2 μm long-channel FDSOI device. When the gate voltage of the device drifts from the zero-temperature coefficient (ZTC) point by ±10%–±20%, the output current change of the short-channel FDSOI device is still the lowest. It is proved by theory and simulation that the low temperature change rate of the carrier velocity of the short-channel FDSOI device is the main factor affecting the stability of the output current. From the analysis of the saturation current model and the ZTC operating point, reducing the gate operating voltage of the device or increasing the threshold voltage of the device can further improve the stability of the output current at high temperatures. The research in this paper proves that the 28 nm UTBB FDSOI device has good high temperature saturation current stability, which can well meet the output current stability requirements of high temperature analog circuits.

The ongoing trend towards miniaturization and increased packaging density has exacerbated the reliability problem of Au-Al heterogeneous metal bonding structures in high-temperature environments, where extreme temperatures and high current pose a serious challenge. In order to address this issue, the present study aims to investigate the electromigration reliability of Au-Al bonding by comparing the conventional heterogeneous contacts with OPM structures, which are homogeneous contacts. A novel bonding layout was developed to precisely detect the resistance and obtain stage changes in electromigration. The experimental results demonstrated that the relative resistance shift of Au-Al bonding at 250 °C was 98.7%, while CrAu and NiPdAu OPM structures exhibited only 46.1% and 2.93% shifts, which suggests that the reliability of OPM structures was improved by a factor of 2.14 and 33.6, respectively. The degradation of Au-Al bonding was attributed to the large cracks observed at the bonding interface and lateral consumption of Al elements. In contrast, OPM structures only exhibited tiny voids and maintained a better bonding state overall, indicating that homogeneous metal contacts have better immunity to electromigration. Furthermore, this study also observed the polarity effect of electromigration and analyzed the impact of NiPdAu thickness on reliability. Overall, this research provides a novel approach and an insightful theoretical reference for addressing the bottleneck of high-temperature electromigration reliability in high-temperature sensor packaging.

Partially depleted silicon-on-insulator (PDSOI) MOSFETs are widely used in 225 °C high-temperature electronic system applications with integrated circuits. But the process node stays at 0.5 µ m for a long time and no further breakthrough can be achieved. This paper reports the high-temperature characteristics of 28 nm ultra-thin body and box fully depleted SOI (FDSOI) CMOS transistors with low threshold voltage (LVT) structure. Experimental results demonstrate that V t shift changes with temperature as low as 0.59 mV °C −1 , the subthreshold slope (SS) is 145.35 mV dec −1 at 300 °C, and the related parameters are optimized by 3.7 times and 2.2 times respectively compared with 0.13 µ m PDSOI. Combined with theoretical analysis, it is proved that the ultra-body FDSOI has an LVT drift rate and better SS than 0.13 µ m PDSOI at high temperature. The advantage of this performance is mainly due to the difference between α VT α VT and β VT coefficients related to the back gate effect. Under negative back-gate bias, the I on / l off ratio can be increased by two orders of magnitude without affecting V t shift changes with temperature, this proves that the FDSOI is capable of high-temperature applications above 300 °C. This paper provides substantial support for future high-temperature system integrated circuits from the micro-scale to the nano-scale.