Electron spin resonance spectroscopy (ESR) of a single electron in planar Si-MOS quantum dot is reported in the vicinity of a valley level anti-crossing. A number of one and two-photon resonances are observed due to mixing of magnetic spin-flip and electric valley-flip transitions. This allows the reconstruction of the energy-level diagram of a four state system with two valley and two spin states. Near the anti-crossing, an enhancement of the Rabi frequency is observed. This is attributed to an electric-dipole transition activated by admixing of the upper energy level due to inter-valley spin coupling. The electric-dipole transition may be driven via capacitive coupling between the ESR antenna, and the confinement gate. To characterize spin-valley coupling responsible for the enhancement, we measure the anisotropy of the g-factor difference between the two valley states, the mean g-factor and the inter-valley spin coupling for both in and out-of-plane magnetic fields. The inter-valley spin coupling is strongly modulated by the direction of the B-field, and is strongest for out-of-plane B-field, consistent with an in-plane spin-valley field. In principle, this strong Electric dipole spin resonance (EDSR) effect could be utilized for fast all-electrical spin control in small-scale devices.

Achieving uniform and scalable control of semiconductor spin qubits remains a key challenge for large scale quantum computing. In this work, we investigate how gate oxide thickness influences uniformity in dense two dimensional silicon quantum dot arrays. Using a 7 x 7 array fabricated in a 300 mm CMOS-process patterned by EUV lithography, we statistically characterize 392 quantum dots across four different oxide thicknesses. The threshold voltages, capacitances, lever arms, and charging energies are extracted using parallel row based measurements and we identify an optimal SiO2 thickness of 17 nm that minimizes threshold voltage variability below 63 mV standard deviation. Our observations illustrate how multiple sources of disorder can introduce competing oxide-thickness dependencies, resulting in non-monotonic trends. These results provide key design guidelines for dense, scalable silicon spin qubit architectures.

Silicon spin qubits are a promising platform for quantum computing due to their high coherence, controllability, and CMOS manufacturability, yet scalable implementations have so far been limited to a few qubits. Here, to take a step towards larger qubit systems, we tune and coherently control an eight-dot linear array of silicon spin qubits fabricated in a 300 mm CMOS-compatible foundry process, establishing operational scalability beyond the two-qubit regime. All eight qubits are successfully tuned and characterized as four double-dot pairs, exhibiting Ramsey dephasing times T 2 * up to 41(2) μs and Hahn-echo coherence times T 2 Hahn up to 1.31(4) ms. Readout of the central four qubits is achieved via a cascaded charge-sensing protocol, enabling high-fidelity measurements of the entire multi-qubit array in a two step process. Additionally, we demonstrate a two-qubit gate operation between adjacent qubits with low phase noise. We show that silicon spin qubit arrays can be scaled to medium-sized arrays of 8 qubits while maintaining system coherence.

The realization of large-scale silicon quantum processors requires spin qubits compatible with advanced semiconductor manufacturing technologies, demanding lithographic processes that combine nanometer-scale precision with exceptional uniformity. Although the highest-performing silicon spin qubits demonstrated to date have relied on electron-beam (e-beam) lithography, its serial exposure process limits reproducibility studies and wafer-scale fabrication. Here, we demonstrate high-performance silicon metal-oxide-semiconductor (SiMOS) spin qubits fabricated using extreme-ultraviolet (EUV) lithography in a 300 mm semiconductor pilot line. We report wafer-scale quantum-dot uniformity metrics, including 100

Spin qubits need to operate within a very precise voltage space around charge state transitions to achieve high-fidelity gates. However, the stability diagrams that allow the identification of the desired charge states are long to acquire. Moreover, the voltage space to search for the desired charge state increases quickly with the number of qubits. Therefore, faster stability diagram acquisitions are needed to scale up a spin qubit quantum processor. Currently, most methods focus on more efficient data sampling. Our approach shows a significant speedup by combining measurement speedup and a reduction in the number of measurements needed to tune a quantum dot device. Using an autotuning algorithm based on a neural network and faster measurements by harnessing the field-programmable gate array embedded in Keysight's Quantum Engineering Toolkit, the measurement time of stability diagrams has been reduced by a factor of 9.8. This led to an acceleration factor of 2.2 for the total initialization time of a SiGe quantum dot into the single-electron regime, which is limited by the Python code execution.

The rate of coherence loss is lower for a qubit under the Rabi drive than a freely evolving qubit T-2(Rabi )> T-2(& lowast;) . Building on this principle, concatenated continuous driving (CCD) keeps the qubit under continuous drive to suppress noise and manipulate dressed states by either phase or amplitude modulation. In this work, we propose a variant of CCD which simultaneously modulates both the amplitude and phase of the driving field to generate a circularly polarized field in the rotating frame of the carrier frequency. This circular-modulated CCD (CMCCD) cancels the counterrotating term in the second rotating frame, eliminating a systematic pulse-area error that arises from an imperfect rotating wave approximation for fast gates. Numerical simulations demonstrate that the proposed CMCCD achieves higher gate fidelity than conventional CCD schemes. We further implement and compare different CCD protocols using an electron spin-qubit in an isotopically purified Si-28-MOS quantum dot and evaluate its robustness by applying static detuning and Rabi frequency errors. The robustness is significantly improved compared with the standard Rabi drive, showing the effectiveness of this scheme for qubit arrays with variation in qubit frequency, coupling to the Rabi drive, and low-frequency noise. The proposed scheme can be applied to various physical systems, including trapped atoms, cold atoms, superconducting qubits, and NV centers.

Understanding phonon and carrier transport in Group-IV alloys is essential for developing high-performance thermoelectric materials compatible with Si-based integration. Herein, we report the growth of p- and n-type Ge1-x Sn x epitaxial layers (x = 0-0.23) on (001)-oriented substrates (Si, Ge, GaAs, and InP) via low-temperature molecular beam epitaxy. Moreover, their thermoelectric properties were systematically characterized at room temperature. Thermal conductivity (kappa) was significantly reduced via Sn alloying and by decreasing the lateral correlation length (), which reflects microscopic lattice tilts induced by strain relaxation. This reduction is attributed to enhanced phonon scattering at domain boundaries, as corroborated by a Boltzmann transport model incorporating alloy, Umklapp, and boundary-scattering mechanisms. kappa decreased from 23.6 (x = 0) to 1.5 W m(-1) K-1 (x = 0.23) and 4.8 to 1.4 W m(-1) K-1 in Ge0.95Sn0.05, with decreasing from 49 to 2.2 nm. Electrical conductivity (sigma) and the Seebeck coefficient (S) were evaluated using high-resistivity substrates, revealing that carrier transport was less sensitive to compared with thermal transport in p-type layers, whereas a strong -dependence appeared in n-type layers. High power factors (PF = S-2 sigma) of 10 and 30 mu W cm(-1) K-2 were achieved at room temperature for p- and n-type Ge-rich Ge1-x Sn x layers (x <= 0.05), respectively. Thus, domain-boundary engineering via lattice tilt control is an effective strategy to suppress kappa while preserving favorable electrical transport, inducing high power density in on-chip thermoelectric generators.

We report the recent progress of waveguide-coupled O-band GeSi quantum confined stark effect electroabsorption modulators, monolithically integrated in a Si photonics platform on 300 mm Silicon-on-insulator wafers with 220 nm thick Si top layer. A wafer-scale analysis of static insertion loss (IL) and extinction ratio (ER) is presented, showing IL down to 7.5 dB with ER of 5 dB for a 36.8 mu m long device, at drive voltages of 2 V peak-to-peak. Modulation bandwidths beyond 50 GHz are demonstrated, with an extracted junction capacitance of 57 fF and series resistance of 8.3 Omega. Finally, open eye diagrams are demonstrated for non-return-to-zero on-off keying (NRZ-OOK) modulation for data rates from 40 Gb/s up to 64 Gb/s, with dynamic extinction ratio of 2.5 dB, at 1320 nm wavelength.

This paper demonstrates the relevance of X-rays for inline metrology and process control of complementary field-effect transistors (CFET). After briefly reviewing the stringent metrology needs of CFET, we focus on the starting epitaxial SiGe/Si multilayer and demonstrate that inline X-ray diffraction (XRD) allows the accurate measurement of every individual thickness and composition of this complex stack. Further, we compare to the performance of inline X-ray reflectivity (XRR), which beyond providing individual thicknesses in angstrom-level agreement with XRD also gives access to elusive information about the roughness of the SiGe/Si interface. Moving along the integration flow, we explore the profiling capabilities of inline grazing-incidence small-angle X-ray scattering (GI-SAXS) after inner spacer lateral recess through simulation and preliminary experiments. As we demonstrate, GI-SAXS provides independent information about width, height and inner spacer cavity depth but would necessitate deeper probing depths and smaller beam footprint to enable CFET metrology. Moving to incident energies lower than the currently used Cu K alpha might solve this issue.

Among the many types of qubit presently being investigated for a future quantum computer, silicon spin qubits with millions of qubits on a single chip are uniquely positioned to enable quantum computing. However, it has not been clear whether the outstanding high-fidelity operations and long coherence times shown by silicon spin qubits fabricated in academic settings1-8 can be reliably reproduced when the qubits are manufactured in a semiconductor foundry9-11. Here we show precise qubit operation of silicon two-qubit devices made with standard semiconductor tooling in a 300-mm foundry environment. Of the key metrics, single- and two-qubit control fidelities exceed 99% for all four devices, and the state preparation and measurement fidelities reach up to 99.9%, as evidenced by gate set tomography. We report spin lifetime and coherence up to T1 = 9.5 s, T 2 * = 40.6 μ s and T 2 Hahn = 1.9 ms . We determine that residual nuclear spin-carrying isotopes contribute substantially to operational errors, identifying further isotopic purification as a clear pathway to even higher performance.

Silicon spin qubits offer long coherence times, a compact footprint and compatibility with industrial CMOS manufacturing. Here, we investigate spin qubits hosted in quantum dots fabricated in a state-of-the-art 300 mm nanoelectronics foundry and demonstrate substantially enhanced coherence, achieving a Hahn-echo time of T_2^Hahn = 4 ms for singlet–triplet oscillations. Employing noise spectroscopy and noise correlation measurements, we identify detuning noise with an amplitude of δε_rms = 2.2 μeV (integrated over 90 s) and observe strong zero-phase correlations between two spatially separated spin qubits. The singlet–triplet basis intrinsically rejects these common-mode fluctuations, yielding a pronounced suppression of dephasing. Our results suggest that exploiting the versatility of silicon quantum dots to adapt the qubit encoding to the microscopic noise landscape represents a promising strategy for advancing scalable quantum information processing.

We demonstrate high-fidelity single qubit control in a natural Si-MOS quantum dot fabricated in an industrial 300 mm wafer process on a silicon on insulator (SOI) wafer using electron spin resonance. A relatively high optimal Rabi frequency of 5 MHz is achieved, dynamically decoupling the electron spin from its 29-Si environment. Tracking the qubit frequency reduces the impact of low frequency noise in the qubit frequency and improves the T^Rabi from 7 to 11 μs at a Rabi frequency of 5 MHz, resulting in Q-factors exceeding 50. Randomized benchmarking returns an average single gate control fidelity of 99.5 ± 0.3

We present an RF equivalent circuit model for GeSi quantum confined stark effect (QCSE) electro-absorption modulator (EAM) integrated in a 300 mm Si photonics platform. The model incorporates two key components: the first captures the contributions from interconnects and bondpads, while the second represents the electrical and optical characteristics of the modulator. The model is validated by fitting it to measured S11 parameters across various EAM lengths under different bias conditions. The derived circuit parameters are subsequently employed to simulate the electro-optic S21 response, successfully estimating the EAM 3dB bandwidth in a good agreement with the measured small-signal modulation response. Additionally, deeper insights about the physical interpretation of the S11 data are obtained by converting the S11 to the impedance (Z) domain. Our model facilitates the analysis of EAM performance under high-speed operation, identifying the limiting factors for further speed enhancement.

After a short description of the evolution of metal-oxide-semiconductor device architectures and the corresponding requirements on epitaxial growth processes, the manuscript describes the material properties of complicated Si/SiGe multi-layer stacks used for complementary field effect transistor (CFET) devices. They contain two different Ge concentrations and have been grown using conventional process gases. A relatively high growth temperature is used to obtain acceptable Si and SiGe growth rates. Still island growth has been suppressed for Ge concentrations up to 40%. Excellent structural and optical material properties of the Si/SiGe multi-layer stack will be reported, with up to 3 + 3 Si channels in the top and bottom part of the stack, respectively. The absence/presence of lattice defects has also been verified by room-temperature photoluminescence measurements. Photoluminescence measurements at low temperatures are used to study band-to-band luminescence from individual sub-layers and to illustrate the optical material quality of the CFET stack.

Epitaxially grown Si/Si1−xGex multi-stacks with ≥100 bilayers (≥200 sublayers) are being considered for three dimensionally vertically stacked dynamic random access memory devices. Because of the lattice mismatch between Si1−xGex and Si, the high total layer thickness, and the need for sharp interfaces, it is challenging to develop a low cost epitaxial growth process. This work describes the material characteristics of multi-stacks containing up to 120 pairs (241 sub-layers) of {65 nm Si/10 nm Si0.8Ge0.2} epitaxially grown on 300 mm Si wafers, with fully strained layer stacks at the inner part of the wafers. This Ge concentration allows a high etching selectivity during selective lateral Si0.8Ge0.2 removal later in the device fabrication. However, misfit dislocations are formed near the rim of the wafer, as the wafer edge lowers the energy barrier to form misfit locations. The drive for layer relaxation is reduced by reducing the lattice mismatch between Si and Si1−xGex. This can be done either by adding carbon into the Si1−xGex or by reducing the Ge concentration in the Si1−xGex layers. It will also be discussed how deposition on the reactor quartz tube might affect the temperature of the growing surface, leading to drifts in both layer-to-layer and within-wafer uniformities, and how these issues can be mitigated.

High speed, highly efficient, ultra-compact, and ther-mally stable modulators are needed to meet the increasing growthin datacenter traffic. This letter demonstrates the temperature-dependent DC performance and reliability study of O-bandGeSi quantum confined stark effect (QCSE) electro-absorptionmodulators (EAM) integrated in a 300 mm silicon photonicsplatform. The modulator with a width of 2 mu m and a lengthof 36.8 mu m demonstrated thermal stability in the measurementrange of 25 degrees C to 75 degrees C, with a mean value of the band edgeshift coefficient of 0.59 nm/degrees C. The optimum extinction ratio (ER)undergoes a red shift and is preserved at higher temperatures.The self-heating of the device due to optical absorption is assessedusing finite element (FE) simulations, and it is found to be<5 K in most operating conditions. Our results emphasize thepromise of the GeSi QCSE EAM for next-generation optical I/Oapplications.

Mg2Si nanosheet bundle (NSB) powders were synthesized via thermal annealing of CaSi2 crystal powders using Mg melt, molten MgCl2, and related salt mixtures, as well as by Mg-MgCl2 vapor-phase synthesis. The compositional, structural, and thermoelectric characteristics of the NSB powders were examined. Using Mg melt, molten MgCl2, and related salt mixtures, Mg2Si NSBs with improved compositional homogeneity and higher electrical conductivity-attributed to the suppression of Mg deficiency-were successfully obtained. In contrast, vapor-phase synthesis produced inhomogeneous Mg2Si with non-uniform Mg distribution. The remarkable improvement in the structural homogeneity and electrical conductivity of the Mg2Si nanosheet bundles synthesized in the liquid phase was discussed in terms of the reactions between Mg and Si in the liquid, and was further attributed to improved surface conditions and the formation of unintentional compounds on nanosheets and particles during liquid-phase synthesis, which facilitated better interparticle contact and charge transport.

Molecular spin qudits offer an attractive platform for quantum memory, combining long coherence times with rich multi-level spin structures. Terbium bis(phthalocyaninato) (TbPc_2) exemplifies such systems, with demonstrated quantum control and chemical reproducibility. In hybrid quantum architectures, TbPc_2 can act as the primary memory element, with semiconductor qubits providing scalable readout and coupling. Here we present a step toward such a hybrid system: using an industrially manufactured silicon metal-oxide-semiconductor (SiMOS) spin qubit to detect electronic spin transitions of an ensemble of TbPc_2 molecules. The readout is based on a compact and robust protocol that applies a microwave pulse while all gate voltages defining the qubit are held at a fixed operating point. This protocol, which combines simultaneous Rapid adiabatic Passage and Spin- Selective tunneling (RPSS), enables high-contrast resonance detection and avoids repeated π-pulse recalibration common in decoupling schemes. By demonstrating ensemble detection, we establish a foundation for integrating molecular quantum memories with industrial qubit platforms and mark an important step toward single-molecule hybrid quantum technologies.

We present an initial thermal study for O-band GeSi quantum confined stark effect electroabsorption modulator on a 300 mm Si photonics platform. High temperature insertion loss, extinction ratio and dark current are presented.