The limit of Parasitic Effects in terms of number of synapses is estimated for phase-change-memory based neuromorphic circuit under scaling technology nodes following ITRS. Parasitic capacitance components are evaluated for a 55nm process and extrapolated to other nodes. A memory compact model is used to study the effects of the capacitance on firing and weight updating in synapses, which provides design constraint for posterior bitline load estimation. The estimated maximum number of synapses indicate decreasing bitline load capacity due to intensified impact of parasitic capacitance along scaling feature size. The proposed estimation methodology is applicable to advanced nodes to provide quick evaluation for neuromorphic circuit design.

Amorphous carbon (APC)/Al laminated composites were prepared by hydrothermal carbon adsorption on plates (HTCAP) and vacuum hot-press sintering process. The effect of the glucose solution concentration on the microstructure, mechanical properties and tribological properties was investigated. The results indicate that APC is uniformly distributed between layers and has good interfacial bonding with the matrix through the diffusion of Al. As the glucose solution concentration increases, the interlayer hardness, ultimate tensile strength and elongation first increase and then decrease, while the wear rate shows the opposite trend and the coefficient of friction (COF) gradually decreases. A maximum elongation of 16.4% and a minimum wear rate of 0.344×10−5 mm3/(N·m) are achieved at a glucose solution concentration of 0.3 mol/L. Adhesive wear is the dominant wear mechanism of APC/Al laminated composites. The improvement in wear resistance is attributed to the formation of uniform APC lubrication film on the wear surface.

Amorphous carbon (APC)/A6061 laminated composite was fabricated by hydrothermal carbonization combined with vacuum hot-press sintering. The microstructure, nano-hardness and tribological properties were investigated. Compared with A6061 plate and A6061 laminated material, the wear rate of this composite is decreased by 37.04% and 49.50%, and the coefficient friction is reduced by 9.09% and 14.89%, respectively, exhibiting excellent wear resistance. At last, the wear resistance mechanism of the APC/A6061 laminated composite was illuminated.

A B4C@amorphous carbon(APC)/Al matrix composite was fabricated by using hydrothermal carbonized deposition on chips(HTCDC)process and solid-state synthesis process.The microstructure and mechan-ical properties of the B4C@APC/Al matrix composite were investigated.After HTCDC process,nano-B4C particles(50 nm)and micron-sized B4C@APC core-shell spheres with a diameter of 2 μm were found in the composites.The microhardness of the micron-sized B4C@APC spheres is 1.66 GPa,which is greater than that of the α-Al matrix(1.06 GPa).Dislocation accumulation is observed around the micron-sized B4C@APC spheres,indicating that the micron-sized B4C@APC spheres have a strengthening effect on theα-Al matrix.Due to the formation of micron-sized B4C@APC spheres,the reinforcement of nano-B4C particles into the composites is transformed from single-sized particle enhancement to bimodal-sized particle enhancement.The strengthening mechanism for B4C@APC/Al matrix composites with bimodal-sized particles of nano-B4C and micron-sized B4C@APC spheres were analyzed,which includes thermal mismatch strengthening generated by the mismatch of coefficient of thermal expansion(CTE)between micron-sized B4C@APC core-shell spheres and α-Al matrix,Orowan strengthening produced by nano-B4C particles,Hall-Petch strengthening and load transfer strengthening produced by the bimodal-sized en-hancement from nano and microspheres.A relationship model between the yield strength(YS)increment and the conversion rate(x)of micron-sized B4C@APC core-shell spheres was estimated.

A compact model of mushroom-type phase change memory (PCM) with parameter extractions is reported in this work. General device physics of heating dynamics, crystallization kinetics and filaments formation are covered in four essential modules. The memory resistances are calculated with the conformal mapping technique, together with corrections for non-ideal geometries. A flow of model parameter extractions is then developed. With a procedure of seven steps, all model parameters are obtained with verifications from experimental PCM prepared with 40nm CMOS process. The model applicability in PCM designs are then demonstrated with Verilog-A implementation and simulation convergences of typical circuits.

A robust simulation framework was developed for nanoscale phase change memory (PCM) cells. Starting from the reaction rate theory, the dynamic nucleation was simulated to capture the evolution of the cluster population. To accommodate the non-uniform critical sizes of nuclei due to the non-isothermal conditions during PCM cell programming, an improved crystallization model was proposed that goes beyond the classical nucleation and growth model. With the above, the incubation period in which the cluster distributions reached their equilibrium was captured beyond the capability of simulations with a steady-state nucleation rate. The implications of the developed simulation method are discussed regarding PCM fast SET programming and retention. This work provides the possibility for further improvement of PCM and integration with CMOS technology.

In this paper, a comparison study between different drain current models including velocity saturation effect for gate-all-around (GAA) MOSFET is performed from the aspect of accuracy and symmetry. A charge-based drain current model with velocity saturation effects by the Caughey- Thomas model with an exponent factor n=2 is developed. Its relationships with the industry standard BSIM-CMG model which assumes an exponent factor n=1 are discussed. 3-D TCAD simulations are performed to benchmark the models' accuracy. It is shown that similar accuracy is achieved with both models while applying an even number in the velocity saturation formula helps improving the model's performance under Gummel symmetry tests.

To reduce the reset voltage and thus leakage current of the cross-point architecture of phase change memory (PCM), a type of 1S1R cell hierarchy with reconfigured electrode capping around the phase change material is explored in this paper. The electro-thermal behavior during the RESET phase transition is mimicked using a finite element model. Results indicate that the temperature distribution, potential drop and current density across the active region can be reshaped. Especially, the process of temperature evolution for phase transition is accelerated and thus the PCM cell can be reset under a lower voltage, e.g., from 2.2 V to 1.2 V for our typical configuration with a GST width of 40 nm and heater width of 20 nm. As a result, the lower RESET voltage decreases the leakage current and power consumption, potentially leading to an increased integration level for cross-point PCM.

An analytical model describing the current-voltage characteristics of modern organic light emitting diodes (OLED) including the temperature effects is reported. OLED operations in different regions are analyzed with emphasis on temperature effects. The increasing carrier concentrations and mobility with temperature mainly contribute to the higher current. The region-wise formulas are connected to form a full-region model. With all parameters originating from the OLED physics, the developed model agree well with experimental OLED data.

Phase change memory (PCM) formed by Ge2Sb2Te5 (GST) on vertical carbon nanotube (CNT) filled contact plug is demonstrated in this paper. In order to achieve compatibility with the underlying process, the CNTs are synthesized using nickel catalyst at a low temperature. Reasonable contact characteristics between the CNTs and GST are achieved without material compatibility problem. Due to the small contact size of the CNT to the phase change material, a significant reduction in programming power is achieved compared to metal contact at the same via size. The temperature simulation result shows that the CNT filled via helps to reduce the programming area. The fabricated PCM on CNT filled via is able to endure more than 104 SET/RESET cycles without observable degradation.

The contact property between Ge2Sb2Te5 (GST) with vertical carbon nanotubes (CNTs) is studied in this work. By careful catalyst design and process optimization, we have demonstrated the formation of ohmic contact between the CNT and the GST material. The developed process is CMOS compatible and can be used for form phase change memory over the vias in the interconnect layers.

Carbon nanotubes (CNTs) and graphene are potential candidates for future interconnect materials. CNTs are promising on-chip via interconnect materials due to their readily formed vertical structures, their current-carrying capacity, which is much larger than existing on-chip interconnect materials such as copper and tungsten, and their demonstrated ability to grow in patterned vias with sub-50 nm widths; meanwhile, graphene is suitable for horizontal interconnects. However, they both present the challenge of having high-resistance contacts with other conductors. An all-carbon structure is proposed in this paper, which can be formed using the same chemical vapor deposition method for both CNTs and graphene. Vertically aligned CNTs are grown directly on graphene with an Fe or Ni catalyst. The structural characteristics of the graphene and the grown CNTs are analyzed using Raman spectroscopy and electron microscopy techniques. The CNT-graphene interface is studied in detail using transmission electron microscopic analysis of the CNT-graphene heterostructure, which suggests C-C bonding between the two materials. Electrical measurement results confirm the existence of both a lateral conduction path within graphene and a vertical conduction path in the CNT-graphene heterostructure, giving further support to the C-C bonding at the CNT-graphene interface and resulting in potential applications for all-carbon interconnects.

In this work, a model is developed for RESET current reduction calculation for phase-change memory (PCM) cell with thermal buffer layer. Numerical simulation indicates more significant contribution of the buffer layer on heat generation than on thermal loss, supporting following model development which treats the total cell resistance as the crucial factor. The model is verified by comparison with both finite element simulation and experimental data, hence is capable to give guidance in future buffer layer design, particularly in estimation for the limit value of current reduction and buffer layer thickness.

The functionality of phase change memory (PCM) as a promising non-volatile memory (NVM) is realized by changing the material properties of phase change (PC) material in a near-bottom-electrode region called ‘active region’. The shape of the active region is usually assumed to be hemispheric as demonstrated by [1][2], based on which some work have been done to calculate the radius for further design optimization [3][4]. However the hemispheric assumption is only valid when the phase change element (PCE) layer, has large enough dimension to satisfy the requirement of semiinfinite thermal conductive medium used to calculate the heat generation [3]. And the dimension of the PCE layer might be small in actual design, in order to reduce the total phase change volume, which will invalidate the hemisphere assumption due to the finite geometry boundary of PCE layer [5]. So far very few work has been reported to include this situation for the calculation although the necessity is evident to develop a more general model to improve the universality of preceding work in 3-D resistance calculation, where active dimension is an indispensable element [6]. For this purpose an analytical model is proposed for active dimension calculation by solving 3-D heat conduction equation in this work, which is applicable to varying cell geometries including the situation without semi-infinite assumption.

Despite the promise for resistive phase-change memory to be used in the BEOL memory integration, achieving low current programming and rapid thermal cycle management are still the main barriers in term of operation. In this work, different methods to reduce the programming current are examined with respect to their effects on thermal cycling during SET and RESET. In particular, the discussion will focus on the engineering of the electrode to phase-change material interface to achieve low programming current. Experimental demonstration and thermal simulation data are used to illustrate the concept and explain the device behaviors.

In this paper, a 3-D resistance model is proposed for phase-change (PC) memory cell based on cell geometry and RESET current. Explicit expression is developed for PC radius in terms of RESET current, cell geometry, and material property. Conformal mappings are used for SET and RESET resistance calculation in 2-D models, which solve the problem of current crowding in structures with complex boundary condition. In the 3-D model development, additional spreading resistance is considered, together with the bulk resistance stemmed from 2-D model to form the eventual complete expression. Models show good consistency with finite element simulation and experimental data.

A methodology to study phase-change memory programming at atomistic level during SET and RESET operations is presented. Based on the melt-quench scheme, the molecular dynamic for amorphization and crystallization of GeTe been investigated. The time evolution of the crystal structure under different annealing and quenching conditions has been demonstrated. The final structure under different SET and RESET conditions can be predicted using the proposed method.