A novel 3D RRAM concept using a stackable multi layer 1TXR memory cell structure is proposed The access transistor is fabricated in silicon which has excellent affinity to the standard CMOS process Using an 8 layer metal of stacked 1TXR (X=64) as an example the density is over 260% higher than that of the conventional single layer 1T1R structure Further a corresponding operation algorithm is put forward which can inhibit effectively mis write and mis read caused by sneaking current and reduce power consumption

This paper reports a novel 3D RRAM concept using stackable multi-layer 1TXR memory cell structure for future high density application. Using an 8-layer metal of stacked 1TXR (X = 64) as an example, the density is over 260% higher than that of the conventional single layer 1T1R structure. Corresponding operation algorithm is put forward for the first time, which can inhibit mis-write and mis-read caused by sneaking current and reduce power consumption.

ABSTRACT A general HSPICE macromodel for the CuxO based resistive random access memory(ReRAM) cell is presented in this paper. It can simulate both the dc and transient behavior of ReRAM cells. The simulation results were compared with the experimental results and exhibited desirable accordance.

A nonvolatile static random access memory (NVSRAM) cell with two back-up CuxO memory devices is proposed in this paper. The manufacturing process is compatible with the standard CMOS process. By adopting a dynamic supply voltage scheme, the proposed cell can work correctly in four different operation modes. Compared with the standard SRAM cell, the proposed cell offers non-volatile storage which allows the unused blocks of SRAM to be powered down to save energy.

ABSTRACT This paper presents a novel self-adaptive wordline voltage generator for phase change memories. It is based on a feedback loop which modulates the output resistance of the select MOS transistors to compensate the voltage drop across the bitline distributive resistance. Simulation results show that very effective compensation is achieved, with the reset current kept constant at the desired value for memory cells located at different rows.

In this paper, Ferroelectric is introduced to nonvolatile programmable logic device (NVPLD). The device system is constructed, and the circuits of three main elements: switch cell, nonvolatile D flip-flop (NVDFF) and configurable logic block (CLB), are presented. Based on the circuit design, the feasibility of this device has been verified.

With the increasing requirement of high density memory technology, a new cell structure—1TR has received much attention. It consists of a single thin film transistor (TFT) with chalcogenide Ge2Sb2Te5 as the channel material. In order to evaluate the feasibility of its application in the field of non-volatile memory, we take a further step in researching on the characteristics of GST-TFT. We fabricated a back-gate GST-TFT and investigated the output and transfer characteristics of its two states. The experimental results show that gate voltage can modulate the GST channel currents in both the amorphous and the crystalline states. Based on the experiments, we can expect that this novel device can ultimately lead to a new nonvolatile memory technology with even higher storage density.