The increasing demand for higher power delivery in high-performance computing (HPC) and AI network devices is driving significant increases in current density per solder interconnects. To fulfill these requirements, Cu-core solder interconnects has been considered as a potential solution for power delivery between the PCB and component, providing enhanced electrical conductivity through a copper core surrounded by a Sn-based alloy shell. Unlike conventional homogeneous Sn-based solder joints, Cu-core interconnects have core–shell configuration and different solder–to-pad interface configurations, which can affect the thermo-mechanical and electro-mechanical behavior and character of the joint. The study presented here investigates the mechanical shear strength and microstructural evolution of Cu-core solder joints under electrical current stressing. In-situ current-stressing shear tests were conducted on 300mm Cu-core solder balls and compared with homogeneous Sn-Ag-Cu solder balls and near-eutectic Sn-Bi low-melting-temperature solder alloys. The results show that homogeneous Sn-Ag-Cu and near-eutectic Sn-Bi solder balls exhibit increased shear strength at intermediate current density conditions but experience degradation at higher current densities. In contrast, Cu-core solder balls demonstrate increasing shear strength with higher current densities, particularly at shorter isothermal aging durations and different behavior under current stressing compared to homogeneous solder joints. These findings indicate that the effect of electrical current stressing in solder interconnects cannot be attributed solely to Joule heating induced temperature rise. Instead, the observed behavior arises from a coupled interaction of localized and time-dependent stress buildup and relaxation at the interface between the solder ball bulk and pad, their interface stability, and temperature and diffusion driven microstructural evolution.

The combined effects of elevated environmental temperature and Joule heating from current stressing are expected to drive elemental migration within solder joints in high-power-demand devices. SAC305 solder exhibited Cu migration along the electron flow direction, while Sn-Bi interconnects exhibited Bi segregation. These elemental migrations can either weaken or strengthen the joint interface at both the anode and cathode sides. Therefore, assessing joint stability under current stressing is crucial for ensuring the long-term reliability of solder interconnects subjected to high electron current flow. This study evaluates the reliability of SAC305 and Sn-Bi-based solder alloys under moderate to high current density conditions to assess their interconnect stability. Shear strength deviations following current stressing were measured along with microstructural evolution under Joule heating-induced temperature rise and current stressing conditions. The solder joints were subjected to a constant current density of 2000 A/cm(2), combined with an applied ambient temperature resulting in an equilibrium joint temperature of 110 degrees C. The associated cross section microstructure of diffusion induced elemental migration samples by current stressing were analyzed, and the current stressed samples were prepared for single-ball shear testing at the package-side interface. Results indicate that SAC305 solder joints exhibit shear strength variations influenced by surface finish and Cu migration direction, whereas Sn-Bi interconnects show variations driven by Bi depletion and accumulation, which occur at either the PCB-side or package-side interface depending on the electron current flow direction. These findings underscore the impact of current density induced elemental migration on the thermo-mechanical stability of solder interconnects, necessitating careful consideration not only for high-current-density applications but also for interconnect reliability under moderate current density conditions. Fracture propagation paths during ball shear testing and long-term reliability of soler joints under current stressing were further discussed through residual stress mapping using electron backscatter diffraction (EBSD) analysis.

Although the thermo-mechanical reliability performance of low melting temperature solder material shows stable performance levels, it is reported that the solder interconnects under higher level of current can cause Bi segregation and degradation in electrical and mechanical stability. Combined with the lower solidus and liquidus temperature, the Joule heating-induced temperature rise at given current density is important to assure the long-term reliability of the solder interconnect. In this study, the solder interconnect Joule heating and its impact on the temperature rise associated with PCB design configuration are identified. The results show that the test board Cu trace and via structure affects the Joule heating-induced temperature rise of the solder joint per given solder alloy configuration. The test set-up enabled the accurate measurement per solder joint via using the temperature coefficient of resistance (TCR), to accurately and directly measure the Joule heating-induced temperature increase per current density condition. Various PCB structure configurations are used in this study utilizing a test PCB with and without VIPPO configuration, representing various thermal dissipation conditions. 300µm solder joints with SAC305, Sn-Bi system low melting temperature solder hybrid (Hybrid LTS), and near eutectic Sn-Bi system low melting temperature solder joints (Full LTS) are current stressed in a range of 0-5000 A/cm 2 in various PCB test structures, which generate different Joule heating-induced temperature increased joint conditions. The results demonstrates that the solder joint with same solder alloy composition and same level of current density show different Joule heating induced temperature increase per PCB configurations. Also, results identifies that the Cu trace at certain current density level needs consideration due to the role of heat sources. The findings presented here indicates that the solder interconnect joule heating needs to be carefully measured to accurately estimate the long-term reliability of the solder joint.

Sn-3.0Ag-0.5Cu (SAC305) is one of the most commonly used Pb-free solder composition nowadays. A minor alloying element addition can improve mechanical properties and thermal reliability of the solder joint. Minor amount of Bithmuth (Bi) or Nickel (Ni) addition can improve mechanical properties of solder by solid solution strengthening, or ensure the structural stability of the intermetalllic compounds. Also, low melting temperature solder with Bithmuth can reduce the cost of soldering process and keep components from deterioration. In this study, reliability of heterogeneous and homogeneous solder joint in the ball-grid-array (BGA) package solder joint were investigated. Using Sn-3.0Ag-0.5Cu (SAC305) solder paste and two kinds of solder balls, we have investigated which combination of solder joint improves the thermo-mechanical reliability. SAC305 and SCN (Sn-0.75Cu-Ni,Bi) balls were used for homogeneous and hetrogeneous joints. Solder balls were attached in BGA package. To examine the solder joint reliability, thermal cycling test was conducted after reflow soldering. Shear strength measurement and cross-sectional analysis of the BGA package solder joints were carried out before and after 2000 cycles of the test. The shear strength of homogeneous solder joint decreased to 68.2% and heterogeneous decreased to 43.5%. The cross-sectional analysis using scanning electorn microscopy (SEM) and electorn back-scattered diffraction (EBSD) showed the (Ni,Cu)6Sn5 and Cu6Sn5 IMCs which were generated in the solder joint, and the crack propagated longer in the homogeneous solder joint of SAC305 after the thermal cycling test. IPFM showed the grain refinement effect of the SCN solder joint after thermal cycling. The minor addition of Bi had played a role as dislocation pinning site and became to equiaxied grain, so that the lifetime of heterogeneous SCN solder joint was superior than that of the SAC305.

To form excellent solder joints in both thermal cycling and drop tests, Sn-2.5Ag-0.8Cu-0.05Ni-1Bi and Sn-0.75Cu-0.065Ni-1.5Bi composition solder balls were developed. In this study, undercooling and solidification characteristics of the alloys, resulting microstructural changes, the solid solution effect of Bi, physical properties, and interfacial reaction properties were investigated and compared with existing solder compositions of SAC305 and SAC1205N. The Sn-2.5Ag-0.8Cu-0.05Ni-1Bi and Sn-0.75Cu-0.065Ni-1.5Bi solders were found to have large undercooling of 38.36 ℃ and 33.38 ℃, respectively. As a result, the Sn-2.5Ag-0.8Cu-0.05Ni-1Bi solder ball had the smallest average size of Sn grains, and the eutectic structures between Sn grains formed relatively small areas and were observed to solidify into fine and uniform structures. Consequently, the total area of the β-Sn phase decreased, while the total area of the eutectic structure relatively increased. Using XRD and STEM analysis, we observed that the addition of a small amount of Bi resulted in a solid solution of the β-Sn phase, which increased the interplanar spacing of certain crystal planes, and contributed to the improvement in mechanical properties such as the hardness of the β-Sn phase. When using the Sn-2.5Ag-0.8Cu-0.05Ni-1Bi solder ball, the intermetallic compound (IMC) layer at the bottom Cu pad interface of the solder joint was relatively thin from right after reflow soldering and maintained a thin thickness throughout the thermal cycling test. The growth suppression property of the IMC layer by Sn-2.5Ag-0.8Cu-0.05Ni-1Bi composition was also confirmed in cases where the paste of this composition was applied to the existing solder ball.

The design-for-security (DFS) methodology protects hardware and systems from physical attacks ON chips while incorporating additional circuits to detect potential security risks. Microprobing and focused-ion-beam (FIB) circuit editing, which are known for their significant invasiveness among physical attacks, are regarded as highly powerful methods to access security-related information directly. The DFS methodology involves continually developing various techniques to defend chips against such attacks. Generally, previous studies compare the arrival times of two signals to detect microprobing and compare the encrypted input–output data to detect circuit editing. In this study, we propose an innovative DFS methodology that records the timings of round-trip signals, which may arrive early or late due to microprobing or FIB circuit editing. This technique can help detect both types of attacks within a single clock cycle while maintaining minimal hardware overhead, even with an increase in the protected area. The proposed methodology considers both miniaturization and security, and it is expected to contribute to the advancement of security-related technologies and strategies.

A fast-growing manufacturing technology of memory devices leads to further increased design complexity, density and test cost. In general, the high cost of automated test equipment (ATE) is required to test the high-speed memory devices, which can exceed its memory performance. To solve this problem, the manufacturers are seeking more cost-effective methods, especially for at-speed testing. In order to reduce the test cost, we propose the instruction-based march test pattern generation scheme which can be applied to the low-end ATE with multiple pattern generators. The proposed method can generate linear patterns based on instructions, which can distribute them to multiple ALPGs of a low-end ATE to implement the high-speed test patterns. The experimental results show that the various march test patterns for at-speed testing can be implemented by using the several fixed commands, regardless of the memory cell sizes.

Alloying effects of Nickel and Bismuth in SAC solder to achieve mechanical and microstructural evolution were investigated by comparing three different chemical composition of solders. Sn-3.0Ag-0.5Cu (SAC305) is the most commonly used for Pb-free solder and solder balls are based on Sn-Ag-Cu alloy composition. Compositions of solder balls were Sn-3.0Ag-0.5Cu (SAC305), Sn-1.2Ag-0.5Cu-0.05Ni (SAC1205N) and Sn-Ag-Cu-Ni-Bi based solder (SACNB). Organic solderability preservative (OSP) surface finished substrate, ball grid array (BGA) package arranged by 300 ㎛ diameter solder ball and Type 4 solder paste were used. Solder ball shear test of the BGA package was conducted before the reflow soldering. Board level package bonding process was carried out by hot air reflow soldering. Void content of the BGA solder joint was investigated after soldering. The microstructure evolution before and after thermal cycle test (TCT) was observed using scanning eletron microscopy (SEM) and energy dispersive spectroscopy (EDS). After TCT, intermetallic compound (IMC) refinement and solid solution strengthening effects of Bi element addition were observed in the solder matrix, and also any segregation of Bi element was not founded. Based on these result, it was found that the solder joint reliability of the middle and low temperature solder joints was improved.

In general, Sn-Ag-Cu solder is widely used for interconnections in semiconductor device packaging. However, recently, several factors have been considered to implement low-melting-temperature solder (LTS), which has a lower assembly temperature than conventional Sn-Ag-Cu solder material. Implementation of LTS solder though has a different driving force per each industry sector. Consumer electronics have a driving force for lower energy consummation towards a carbon net zero strategy compared to the high-performance chip industry sector, which has a different reason based on larger component size-induced challenges, like dynamic warpage. This is a deformation of printed circuit board (PCB) and package components during the reflow process by elevated temperatures. The behavior of dynamic component changes the package size, material characteristics, and temperature range. Although most of the LTS are based on the low-melting-temperature range of 130–140°C, a separate category of intermediate LTS is formed at around 180–190°C to target an assembly peak temperature of 200–210°C. The study presented here targets a LTS at an intermediate temperature assembly to avoid the most active dynamic warpage temperature region. LTS has significant benefits with less warpage and thermal damage towards the component and assembled board, due to the low reflow peak temperature. To improve the thermal cycling performance by maintaining a low melting temperature, a small amount of indium is used as a microalloy element, with 12 mm × 12 mm ball grid array components on 62-mil-thick boards thermal cycled from − 40°C to 125°C with Sn-based LTS including In and Bi. The microstructure changes during thermal cycling have been observed and electron-backscattered diffraction has been used to find a correlation between crack propagation and localized recrystallization. It was found that the added indium enhanced the thermal cycling performance compared to conventional Sn-Ag-Cu-based solders. To compare the paste-induced composition change which dilutes the indium-containing solder ball, a flux-only assembly has been compared.

Use of low melting temperature solder (LTS) materials in interconnect devices is a recent application as they lower the challenges of high reflow peak temperature-induced package warpage during assembly. A good candidate to overcome this challenge is a eutectic Sn-Bi system solder, with a melting temperature of 138°C and a reflow peak assembly temperature of around 185°C. However, Bi causes joint hardening and is prone to brittle fractures under mechanical bend and shock. Therefore, it is critical to understand mechanical properties of Sn-58Bi solder joints under conditions of end-use condition and applications. In this study, a series of isothermally aged 300-μm-diameter solder balls attached to a NiAu pad surface finish, are subject to single-ball shear tests after up to 500 h aging at room temperature, 100°C and −25°C. Single-ball shear tests were performed using a multi-bond tester with 10-μm shear height and two shear speed condition, 10 μm/s and 100 μm/s. The maximum shear load and the distance to the peak shear load were measured to observe the deformation behavior change. Comparative testing was also conducted for Sn-1.0Ag-0.5Cu (wt.%) aged samples for comparison. A decrease in maximum shear strength and loss of ductility with 100°C isothermal aging, opposite to an increase in ductility with room temperature isothermal aging were observed. Isothermally aged Sn-58Bi samples reveal further loss of ductility compared to SAC105 which show increase in ductility. This phenomenon is due to the increased Bi solubility into Sn at a higher temperature range. The deformation behavior for both Sn-58Bi and SAC105 were observed and discussed on partially sheared solder joints using EBSD analysis.

Built-off self-test (BOST) is a widely used technique to reduce the test cost. It makes it possible to test high-speed dynamic random-access memory (DRAM) without using a costly high-performance automatic test equipment (ATE). However, the currently used BOSTs require many ATE connection pins, which degrade the cost reduction effect. In this article, we propose a novel reduced-pin-count BOST to reduce the test cost. The proposed BOST uses bidirectional pins to employ the pins as efficiently as possible. Thus, even if the same amount of data is transferred, fewer pins are required than the previous BOSTs. In addition, it reduces the amount of output data by sending only the information necessary for a DRAM repair process. This is possible because the DRAM repair process requires only the location information of some faulty cells. Therefore, the proposed BOST can send output data with fewer pins compared with the previous BOSTs. Experimental results indicate that the proposed BOST can test high-speed DRAMs using a few ATE connection pins.

With the increase of interest in low melting temperature solder alloys, in recent studies on Sn-Bi based system solder show relatively good thermal cycling performances comparable to conventional Sn-Ag-Cu based solder interconnects at a given thermal cycling profile. Sn-Bi eutectic system microstructures are similar to Sn-Pb eutectic microstructure but have different damage accumulation mechanism due to Bi crystal lattice with Rhombohedral A7 unit cell structure, which is less ductile compared to Sn-Pb, where Pb has face centered cubic crystal lattice. The nature of less ductility in Sn-Bi alloy system reveals a different damage accumulation process during thermal cycling compared to Sn-Ag-Cu solder material, although the thermal cycling performance is comparable with micro-elementalloying. To identify the degradation mechanism in Sn-Bi solder interconnects, the study presented here is a series of microstructure analysis on segmented thermal cycling completed components, which reveal gradual and localized microstructure evolution. 12x12 mm 2 chip array BGA (CABGA) components were thermal cycled with a -40 to 100°C cycle profile and a 10min dwell time. The microstructure developments per component were analyzed with 200-250 cycles interval cross-sections until both Sn- Ag-Cu and Sn-Bi solder joints reached to full failure. The correlation between crack initiation, crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and Electron- backscattered diffraction (EBSD) based strain and residual stress analysis. The analysis revealed the potential damage accumulation process in Sn-Bi solder joint under thermal cycling, which is discussed in this paper.

With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of multi-site testing efficiency owing to the limited number of tester I/Os and power capacity. In this paper, we present an advanced low pin count test architecture for efficient multi-site testing in semiconductors. To achieve this, the scan chain routing method is first exploited to reduce the power consumption during scan-based testing through a cluster-based approach, which is compatible with the test compression architecture. Subsequently, a new test compression architecture is proposed to encode test patterns and enable the testing of each device-under-test (DUT) through a low input test pin count by using the unique properties of the proposed tri-state detector and boundary scan architecture. The experimental results show the decrease in the test I/O requirements and test power consumption. Based on these improvements, the test application time (TAT) was significantly reduced for ISCAS’89 and IWLS’05 OpenCores benchmark circuits compared to the previous methods, without a heavy burden on the additional H/W area and routing overhead.

The current growth of micro-semiconductor technologies requires that an effective solution be found to address the yield and reliability issues associated with embedded memories. A common solution is built-in redundancy analysis (BIRA), which is utilized to guarantee reasonable memory yields. The most common form of BIRA is a module that stores and analyzes fault addresses with a 2-D spare architecture. When the performance of BIRA is evaluated, numerous different parameters are considered, such as repair rate, area overhead, and analysis speed. Because there is a tradeoff between these criteria, many BIRA approaches have been studied so that an ideal BIRA can be found. A novel BIRA approach that focuses on a 100% repair rate and a minimal area overhead is proposed in this paper. In the fault collection phase, the proposed BIRA stores only the essential part of fault addresses in content addressable memories (CAMs), with the rest of the fault addresses being stored in spare memories. After the fault collection phase, a redundancy analysis procedure is performed with the minimum amount of fault information that is stored in the proposed CAM structure. By doing so, the proposed BIRA algorithm can repair all repairable faulty memories while maintaining a minimal area overhead. Our experimental results confirm that the proposed approach exhibits outstanding performance for area overhead, especially when compared to other BIRA approaches that have 100% repair rates.

As the traditional IC design migrates to three-dimensional integrated circuits (3D-ICs) design, new challenges need to be considered carefully to solve its reliability and yield issues. 3D-ICs using through-silicon-vias (TSVs) can have latent defects such as resistive open and bridge defects, which are caused by the thermal stress during the fabrication process. These latent defects lead to the deterioration of the electrical performance of TSVs caused by an undesired increase in the resistance-capacitance (RC) delay. For this reason, various post-bond test methodologies have been studied to improve the reliability of 3D-ICs. Cost reduction in these TSV test architectures is also currently being studied by decreasing various factors such as hardware overhead, test time, and the peak current consumption. Usually, a single test-clock-period is required to determine whether the test result contains the defective TSV. When the test result of any TSVs fails, we use another single test-clock-period to classify its defect type. In this paper, we propose a new TSV test architecture to transfer the combined test output of the test result and the specific defect type to the pad during the single test-clock-period. Our proposed test architecture also provides a reliable block-based concurrent testing to optimize the test time by dividing the die into concurrent blocks. The experimental results showed that our proposed test architecture could reduce the test time and the hardware overhead substantially by ensuring that the reasonable peak power consumption for mass production was reasonable without the test quality being adversely affected.

In this paper, a design for debug (DFD) method that reuses test resources is proposed to reduce the debug cost in post-silicon validation. With the proposed method, the trace buffer is shared for embedded cores to capture the signatures of each core concurrently by reusing a test access mechanism. In this case, the depth of the trace buffer allocated to the core is reconfigurable and variable according to debug scheme. The experimental results indicate that the proposed DFD significantly reduces the debug time when the trace buffer is shared by cores in various debug cases.

As a rapid progress in technology processes, the design integration of high-performance system-on-chip (SoC) is on the rise rapidly. To incorporate hundreds of IP cores into a single chip, a modern SoC exceeds ten million gates with a large number of scan cells, so that it leads excessive energy consumption. In this paper, we present an energy-quality (EQ) scalable scan test method using new scan chain reordering. The method conducts three stages, which are a new scan partitioning, a scan partition-based X-filling, and a statistic-based scan stitching to reduce test energy consumption without quality degradation. The proposed scan partitioning method prevents excessive routing overhead. Then, the proposed scan chain reordering is performed by a statistical analysis considering EQ scalability. It also covers two frequently-used fault models: 1) stuck-at and 2) transition delay. The experimental results show that the proposed scan chain reordering method achieved lower energy consumption and relieve the routing overhead on ISCAS’89, ITC’99, and IWLS’05 OpenCores benchmark circuits in most cases compared with previously existing methods without excessive runtime overhead.