This study provides an insight into the impact of thin purely undoped GaN channel thickness (tch) on surface-related trapping effects in AlGaN/GaN high electron mobility transistors. Our TCAD study suggests that in cases where parasitic gate leakage is the driving trapping mechanism that promotes the injection of electrons from the Schottky gate contact into surface states, this effect can be alleviated by reducing tch of the undoped GaN channel. We show that by decreasing tch from 130 to 10 nm, devices exhibit a reduction in gate-related current collapse under the specific class-B RF operating bias conditions as a consequence of a substantial decrease in the off-state gate leakage with reducing tch. Large-signal simulations revealed an increase by 3 W mm-1 and about 12% output power and power-added efficiency due to the decrease of gate-related collapse. This work, for the first time, highlights the role of a proper purely undoped GaN tch selection to alleviate gate-related surface trapping in the design of GaN-based microwave power amplifiers.

GaN HEMTs are known to suffer from trapping effects that lead to a reduction in current density depending on previously applied drain voltages. Characterization of the effect currently requires expensive fast-pulsed voltage supplies that can be synchronized with measurement. We propose a method that provides basically the same information based on a dynamic load-line measurement in the lower MHz range, speeding up the measurement process and reducing equipment cost. This paper presents a case study based on simulation of a proven advanced GaN HEMT model in order to explore the general feasibility of the concept.

Drain lag is a well‐known phenomenon that leads to radio frequency performance degradation in AlGaN/GaN high‐electron‐mobility transistors. Herein, it is demonstrated that a reduction of the gate‐to‐drain distance (Lgd) from 2.0 to 0.5 μm results in 7% reduction in the current collapse. This improvement is attributed to a decrease in surface trapping, which, in this case, is found to have a greater impact on current collapse than relatively slow traps in the buffer layer. To support this argument, TCAD simulations are conducted. Load‐pull analysis confirms that scaling the devices to Lgd = 0.5 μm provides 15% better output power density at 10 GHz than Lgd = 2.0 μm. Additionally, a new passivation layer for reduced surface traps exhibits a 20 to 30% higher output power density and at least a 10% improvement in power‐added efficiency at 20 GHz on a nominally identical GaN‐on‐semi‐insulating SiC epi‐wafer.

The omission of slow gate-induced electron trapping from compact models significantly weakens their accuracy when utilized in the design of GaN-based robust low-noise and pulsed power amplifiers (PAs). Given the highly negative gate voltage and diverse off-periods inherent in these systems, providing an accurate description of trap time constants becomes paramount. This study deals with this problem by introducing a novel trap implementation suitable for large-signal models, particularly well-suited for those based on physics. Following the Shockley–Read–Hall (SRH) statistics, the proposed model emulates the bias and temperature dependencies of the trap time constants. Furthermore, the inclusion of new model parameter scaling functions covers a broad range of biases. The final model excels in accurately reproducing slow gate-induced and fast drain-induced electron trapping. Rigorous simulations of drain current recovery measurements under various conditions validate the high performance of the proposed trap description. Finally, the study calculates and presents electron capture time constants for gate and drain lag.

Accurate prediction of the large-signal power performance of gallium nitride (GaN) high electron mobility transistors (HEMTs) can be achieved by combining TCAD device modeling with the RF simulations of a physics-based compact model, equipped with a precise trap description. A TCAD computational framework well-calibrated with small-signal and drain-lag measurements from an AlGaN/GaN device served as an input for compact model extraction. The validity of the approach is confirmed through comparison with measurements on devices with different dimensions and locations on the wafer.

This article proposes a novel modeling approach for the analysis of the microwave power performance of GaN HEMTs. By combining Technology Computer-Aided Design (TCAD) physical and circuit design standard compact trap models, surface and buffer traps can be directly correlated, for the first time, with power-added efficiency (PAE) and output power ( $\textit{P}_\text{out}$ ). A new trap model topology is created with an RC subnetwork and nonlinear scaling functions, encouraged by TCAD analysis on trap localization. The effects of surface trapping were quantified using a TCAD-based extraction of the proposed trap model, observing a loss on $\textit{P}_\text{out}$ of 3 dBm and a maximum PAE ( $\text{PAE}_\text{MAX}$ ) loss of 12% due to surface traps. In addition, the correlation of 2-D electron gas (2DEG) at the drain access region with $\text{PAE}_\text{MAX}$ and the 1-dB compression point of $\textit{P}_\text{out}$ ( $\text{OP}_\text{1\,dB}$ ) is investigated and transformed into a correlation between the density of traps ( $\textit{N}_\text{T}$ ) and $\text{PAE}_\text{MAX}$ and $\text{OP}_\text{1\,dB}$ , creating a new direct method to connect TCAD with RF large-signal simulations.

This paper proposes a new method for compact modeling the virtual gate effect by adapting the gate current in the extraction procedure. Drain resistance (R D ) of gallium nitride (GaN) high-electron-mobility transistors (HEMTs) is dynamically varied by time-dependent trapping effects, demanding a high number of measurements for its accurate modeling in scaling-based drain-lag models. We implement insights from physical analysis of the virtual gate effect to make the extraction more efficient and trustworthy. The dynamic R D extraction is based on a simple dc gate current measurement to emulate its cumbersome nonlinear relation with the drain to source voltage (V DS ). RF large-signal simulations with various cases of R D modeling are compared, confirming the accuracy of the presented method.

The parasitic gate tunnelling of electrons into surface traps is shown to be responsible for the current collapse in GaN high electron mobility transistors. Simulations with and without surface traps are compared to pulsed output and gate leakage measurements and showed that the detrimental effect of surface traps is evident at positive gate voltages. Moreover, an apparent relationship between 2-dimensional electron density and Schottky reverse gate current is revealed in the presence of surface traps.

Despite that organic-inorganic lead halide perovskites have attracted enormous scientific attention for energy conversion applications over the recent years, the influence of temperature and the type of the employed hole transport layer (HTL) on the charge carrier dynamics and recombination processes in perovskite photovoltaic devices is still largely unexplored. In particular, significant knowledge is missing on how these crucial parameters for radiative and non-radiative recombinations, as well as for efficient charge extraction vary among different perovskite crystalline phases that are induced by temperature variation. Herein, we perform micro photoluminescence (μPL) and ultrafast time resolved transient absorption spectroscopy (TAS) in Glass/Perovskite and two different Glass/ITO/HTL/Perovskite configurations at temperatures below room temperature, in order to probe the charge carrier dynamics of different perovskite crystalline phases, while considering also the effect of the employed HTL polymer. Namely, CH3NH3PbI3 films were deposited on Glass, PEDOT:PSS and PTAA polymers, and the developed Glass/CH3NH3PbI3 and Glass/ITO/HTL/CH3NH3PbI3 architectures were studied from 85 K up to 215 K in order to explore the charge extraction dynamics of the CH3NH3PbI3 orthorhombic and tetragonal crystalline phases. It is observed an unusual blueshift of the bandgap with temperature and the dual emission at temperature below of 100 K and also, that the charge carrier dynamics, as expressed by hole injection times and free carrier recombination rates, are strongly depended on the actual pervoskite crystal phase, as well as, from the selected hole transport material.

Trap-induced dispersive effects play an important role in PAs and robust LNAs based on AlGaN/GaN-HEMTs. In this paper, the influence of scaling gate-source (GS) and gate-drain (GD) separation is studied through pulsed DC measurements and TCAD physical device simulations. In view of PA-applications, dynamic on-resistance and drain current in the knee region after high drain voltage stress are investigated. The de-embedding of pure scaling effects shows that adverse effects due to trapping are largely independent of the transistor GS/GD separation. Likewise, with regard to robust LNAs, the shift of threshold voltage under large negative gate voltages, typical for RF input overdrive conditions, shows a strong dependence on quiescent stress, but not on device scaling. This is in line with TCAD physical device simulations which suggest that trapping of electrons as well as the extension of the depletion region is affected mainly by the heterostructure and trap properties but not GS or GD separation. The findings aid RF designers to optimize the performance and reliability of GaN-MMICs for the specific application.

Inverted perovskite solar cells (PSCs) have attracted much interest due to their improved operational stability in the past few years. However, despite the recent advances of their performance, they still suffer from low power conversion efficiencies with a reduced open-circuit voltage (V-oc), as compared to PSCs with a regular structure, due to the presence of defect states. In this work, a promising and more effective strategy than the typical post-treatment passivation method is demonstrated for the decrease of nonradiative recombination in quadruple-cation R(b)C(s)MAFA inverted PSCs, through the employment of phenethylammonium iodide in the anti-solvent deposition step during the perovskite formation. As a result, a V-oc value as high as 1.17 V is achieved, while control devices (where the typical chlorobenzene anti-solvent was used) exhibited a significantly lower V-oc of 1.09 V. Additionally, the devices exhibited high moisture stability by maintaining nearly 80% of their initial efficiency for over 500 h exposure in ambient conditions.

The effects of InN layer thickness (4/7/10 nm) in metal–insulator–semiconductor Ni/SiNx/InN structures have been evaluated. The 7 nm thick SiNx layer is deposited in situ, by plasma assisted molecular beam epitaxy, on the surface of InN grown on GaN (0001) buffer layers. Metal–insulator–semiconductor capacitors (MISCAPs) and InN channel field-effect transistors (MISFETs) were fabricated and the electrical characteristics of the devices were studied and discussed. Room temperature current versus voltage analysis of the MISCAPs suggested ohmic conduction by hopping at low electric fields, while field emission was prevailed for high electric fields with an extracted trap barrier height in the range of 1.1–1.3 eV for all the structures. The output characteristics of the fabricated MISFETs showed modulation of the drain–source current with the highest current density of 0.8 A/mm for the 10 nm InN layer, but the channel could not fully pinch-off.