Communication among field-programmable gate arrays (FPGAs) is an important issue in hardware implementations of spiking neural networks because spike events must preserve both firing-time and source-neuron information across multiple devices. The asynchronous pulse code multiple access (APCMA) encoding/decoding method and pulse-code construction are adopted from prior work. The contribution of this study is the design and implementation of a complete liquid state machine (LSM) whose computation is distributed over five compute FPGAs, with one additional communication-only FPGA implementing the hub function. Spikes from the input and recurrent-reservoir neurons are conveyed through APCMA codes to downstream reservoir and readout neurons without global clock synchronization or arbiter control. Environmental-data-based emotion estimation is used as an application-level evaluation task for the implemented system. To process slowly varying environmental data, the per-step input presentation time is adjusted according to the fading memory of the reservoir. In addition, independent readout layers are introduced for the Valence and Arousal axes to reflect the continuous structure of emotion labels. Experimental results using real environmental sensor data show that the proposed estimation structure achieves an accuracy of 86.2%, exceeding the 74.2% accuracy of a conventional four-class LSM baseline. Under margin-based evaluation considering label uncertainty near class boundaries, the accuracy reaches 90.1%. A previous convolutional neural network–long short-term memory (CNN-LSTM) method reported approximately 90% on the same dataset, although its data split and evaluation protocol may differ. These results demonstrate that the APCMA-based multi-FPGA LSM can process real sensor-derived spike trains and achieve competitive estimation performance while maintaining a hardware-oriented readout-training structure.
This paper presents the silicon characterization and synthesis-assisted implementation of a 0.3-V ultra-low-power inverter-based OTA. Evolving from logic-like transconductors, digital-based OTAs (DIG-OTAs) increasingly use standard-cell-oriented architectures to enable reusable and automated implementation flows. The proposed circuit combines a custom Muller-C input stage with standard-cell inverter-based common-mode feedback (CMFB) and differential-to-single-ended (D2S) blocks. Fabricated in TSMC 180-nm CMOS, the OTA occupies 878.39 μm2 and dissipates 5.733nW (19.11 nA) at 0.3V. Room-temperature measurements on one bonded DUT show 44.3-dB open-loop gain, 4.57-kHz gain-bandwidth product with CL = 110 pF, 51.6° phase margin, CMRR=60.3 dB, and PSRR=32.9 dB at 1 Hz. The average slew rate is 0.583 V/ms and THD is 1.05% at 1 kHz for a 100-mV-peak input. The corresponding FOMS is 87.69 kHz·pF/nW. Post-layout PVT, process-corner, and 1000-run Monte Carlo mismatch analyses quantify variability. The implementation maps nine library-inverter instances and two custom Muller-C macros through logic synthesis and automated place-and-route.
The transition to Post-Quantum Cryptography (PQC) introduces substantial computational overhead, particularly for hash-based signature schemes such as Leighton–Micali Signature (LMS), which strain the limited compute, latency, and energy budgets of embedded systems. This paper presents HAMLET, an FPGA-based accelerator for LMS signature generation and verification, integrated with software in a HW/SW co-design on embedded platforms. The proposed architecture targets the dominant bottleneck, namely Winternitz chain evaluation, and exploits chain-level parallelism through a configurable array of SHA-256 cores controlled by a dynamic scheduler. The degree of parallelism is tunable, enabling exploration of performance–area trade-offs under different LMS parameter sets. To enable a fair and system-relevant comparison, the reference LMS implementation is integrated with the accelerator via a Direct Memory Access (DMA)-based Advanced eXtensible Interface (AXI) interface on a PYNQ-Z2 SoC, so that measured latencies include both processing system (PS)–programmable logic (PL) data movement and kernel execution. A system-level evaluation shows that the proposed co-design reduces the LMS Winternitz-chain and Kc kernel latency by up to 26×, and the corresponding kernel-plus-DMA execution time by close to an order of magnitude, compared to a software-only baseline. Shorter execution times also translate into substantial energy savings per signature, confirming the viability of Field-Programmable Gate Array (FPGA)-based acceleration for practical LMS deployment in embedded Post-Quantum (PQ) cryptographic systems.
This paper presents the design, implementation, and silicon characterization of a RISC-V Microprocessor based on the RV32I Instruction Set Architecture (ISA), fabricated in a 28 nm Bulk CMOS technology node. To lay the foundation for high-reliability applications, the digital synthesis and verification flow relies on a radiation-aware methodology and a CAD-based Multi-Corner Multi-Mode (MCMM) framework. The physical layout integrates a high-density Power-Grid architecture engineered to bound the maximum IR-Drop to 39 mV, establishing a robust baseline against voltage transients. This methodology effectively constrains the full macro to a silicon footprint of 0.05 mm2, with the RV32I logic core alone occupying just 0.010 mm2 (13.649 kGE) at a 100 MHz operating frequency. A key contribution of this work is the instruction-level power profiling conducted through 39 dedicated firmware routines, enabling a granular correlation between simulation and baseline experimental measurements. Post-layout Signoff analyses, incorporating conservative power margins, confirm the efficacy of the integrated leakage-mitigation techniques. Experimental results demonstrate a de-embedded core static current of 0.01 mA (extracted from a raw measurement of 0.053 mA, compared to a simulated 0.011 mA) and a dynamic current of 1.81 mA (1.776 mA simulated) at 0.9 V. This results in an energy efficiency of 16.287 pJ/instruction (15.988 pJ/instruction simulated). Notably, the static current accounts for less than 1% of the dynamic consumption, validating the robustness of the digital flow against the inherent leakage of scaled Bulk CMOS nodes. Comparative analysis reveals that the proposed implementation is highly competitive with existing state-of-the-art solutions, establishing a solid characterized baseline for future environmental testing.
This paper presents a tunable parametric notch filter based on a double-pump parametric-mixing architecture that enables on-chip Q-enhancement. A primary pump generates a frequency-dependent positive conductance at the signal frequency, producing a tunable absorption notch, while a secondary pump introduces negative resistance at the idler frequency to compensate resonator loss and enhance selectivity. This mechanism, referred to as parametric mixing, enables active control of the effective quality factor of the idler resonance without external high-Q components. The proposed architecture is implemented as a fully integrated GaAs MMIC and operates over a tuning range of 1.3-2.1 GHz. Measurements show that single-pump operation produces a tunable notch with 4.5-6 dB attenuation, while activation of the second pump increases the notch depth to 13.5-25 dB and reduces the fractional bandwidth to 5.5-6.5%, consistent with Q-enhanced behavior. The device also exhibits a low-loss through response when both pumps are disabled, enabling a true notch-off state. Measured S-parameters show that the double-pump operation substantially improves notch depth and fractional bandwidth, while simulation-based effective-Q extraction supports the interpretation that this improvement results from idler loss compensation, providing a compact and scalable solution for high-selectivity reconfigurable RF filtering.
