Edge-AI workloads increasingly require flexible numerical representations to balance accuracy, energy efficiency (EEF), and hardware utilization. However, the tendency to optimize compute-in-memory (CIM) architectures for a specific numerical format or workload limits their adaptability to alternative integer (INT), floating-point (FP), microscaling (MX), and logarithmic number system (LNS) computation schemes. This article presents a versatile-format, dual-representation gain-cell (GC) CIM accelerator (VF-DR GC-CIM) with support for INT, FP, MX, and LNS multiply-and-accumulate (MAC) operations within a reconfigurable CIM architecture. To ensure numerical flexibility and workload adaptability, the proposed design jointly supports 2’s-complement and sign-magnitude (SM) representations, adaptive MX processing, and LNS-compatible computation. In addition, a dataflow-friendly reconfigurable scheduler reduces the movement of intermediate data in Transformer and Mamba workloads. In a 16-nm 108-kb GC CIM, the proposed accelerator achieved EEF of 120.5 TFLOPS/W with throughput density of 3.18 TOPS/mm ${}^{2}$ in MXINT8 mode.
This article presents a direct-drive coherent optical transmitter (OTX) based on a compact, energy-efficient O-band Mach–Zehnder modulator (MZM) utilizing 400- $\mu $ m-long carrier-injection mode forward-biased p-i-n-junction phase shifters driven in a lumped fashion by a monolithically integrated two-stage electrical driver. The electrical data path employs shunt inductive peaking to achieve 40-GHz driver bandwidth. Passive RC equalization is used to extend the electro-optic (EO) bandwidth of the p-i-n phase shifter-based MZM (PIN-MZM). Fabricated in a 45-nm CMOS-SOI process, the monolithic OTX die is co-packaged with a host serializer–deserializers (SerDes) chip providing high-speed non-return-to-zero (NRZ) and four-level pulse amplitude modulation (PAM4) data. For intensity modulation direct-detection (IMDD) operation with 9 dBm of 1310-nm laser power and transmit pre-emphasis, the 53-Gb/s NRZ and 106-Gb/s PAM4 raw eye-diagrams exhibit optical modulation amplitudes (OMAs) of −2.2 and −2.5 dBm, respectively, with the PAM4 result requiring additional scope feed-forward equalization (FFE). The OTX consumes 93 mW for 106-Gb/s PAM4 IMDD and 194 mW for 212-Gb/s coherent quadrature amplitude modulation (QAM-16) operation, yielding electrical power efficiencies of 0.88 and 0.91 pJ/bit, respectively, with an active die area of 0.612 mm2. Compared to a conventional traveling-wave (TW) MZM fabricated on the same chip with $5\times $ greater die area, the proposed PIN-MZM OTX achieves the same transmit OMA at $2.7\times $ lower laser power for 106-Gb/s PAM4 operation.
A high-efficiency Colpitts DCO-PA with implicit receiver (RX) clock generation for Bluetooth Low Energy (BLE) transceivers (TRXs) using a mode-switching technique is proposed. It features: 1) differential-mode (DM)-to-/common-mode (CM) mode switching that enables DM-only oscillating-PA for a highly efficient 2.4-GHz TX with Q-enhancement, and CM-only oscillation for RX local oscillator (LO) that suppresses TX port residual leakage; and 2) a capacitor-feedback gate-to-drain (GD) Colpitts DCO-PA that avoids signal swing at the source node of the transistor for improved TX efficiency. Fabricated in 28-nm-CMOS, the open-loop DCO-PA achieves a measured system efficiency of 29.4% (31.92%) at 0 dBm (2 dBm) $P_{\mathrm {RF}}$ . When switching to RX mode, it can generate a 4.8-GHz carrier with a −118.5-dBc/Hz phase noise (PN) at 2.5-MHz offset, consuming 2.9-mW power while showing −46.7-dBm TX port residual leakage.
An all-digital variation-tolerant clock duty-cycle control system called VITAMIN is proposed to mitigate the adverse impact of aging-induced duty-cycle distortion (DCD) on the minimum operating voltage ( $\mathrm{V}_{\min }$ ) for energy-efficient processors. Central to the VITAMIN architecture is a monitoring-enabled duty-cycle adjuster (DCA), which employs a time-division multiplexing scheme to reconfigure a unified phase extender (PE) for both duty-cycle measurement and correction. By strictly utilizing identical delay elements for these dual operations, the design solves the delay consistency issues inherent in heterogeneous monitors and adjusters, fundamentally resolving process, voltage, temperature, and aging (PVTA) mismatches at the circuit level. This approach eliminates the associated mapping calibration while minimizing area and power overhead. Moreover, unlike conventional approaches that directly measure clock-leaf nodes, VITAMIN employs a clock-tree replica (CTR) and a critical-path replica (CPR) to enable non-intrusive DCD monitoring and timing-aware duty-cycle control activation. Implemented in a 22-nm four-core RISC-V processor, silicon accelerated-stress chip measurements demonstrate that the system effectively mitigates clock DCD and aging-induced Vmin degradation by up to 5.34% at 200 MHz and 9.04% at 350 MHz, with an area overhead of 0.5% and a power consumption of 4.8%.
Lung diseases significantly impact human health, and using deep neural networks (DNNs) to diagnose related conditions through lung sounds is an emerging trend. Many existing methods focus on direct fine-grained multi-category classification, leading to redundant computation and low energy efficiency in most subject cases with normal lung sound events. Additionally, previous lung sound processors either directly use generic deep-learning intellectual property (IP) cores or lack data reuse, resulting in high hardware overhead or low energy efficiency, respectively. This article proposes an energy-efficient lung sound processor with a two-stage coarse-to-fine DNN model, effectively filtering normal lung sound events before fine-grained classification to reduce unnecessary energy consumption. Three key technologies are as follows: 1) an operator-disparity-driven reconfigurable computing architecture with a dual-mode systolic data flow to accelerate various DNN operators, reducing hardware overhead and improving energy efficiency; 2) a multi-branch hybrid-driven memory architecture to maximize the high energy efficiency inherent in the two-stage hybrid model; and 3)a large-stride layer optimization method to improve hardware utilization and reduce latency. The design is validated on a 16-nm field-programmable gate array (FPGA) platform, consuming 0.39 mJ/frame for normal lung sounds and 2.06 mJ/frame for abnormal lung sounds, improving the energy efficiency by $5.28\times $ in most cases with normal events. A 55-nm test chip is then fabricated, which is the first lung sound artificial intelligence (AI) processor ASIC chip as far as we know from the literature, achieving a high energy efficiency of 2.76 pJ/op at 1.0 V.
