ARCHYTAS aims to design and evaluate nonconventional hardware accelerators, in particular, optoelectronic, volatile and non-volatile processing-in-memory, and neuromorphic, to tackle the power, efficiency, and scalability bottlenecks of AI with an emphasis on defense use cases (e.g., autonomous vehicles, surveillance drones, maritime and space platforms). In this paper, we present the system architecture and software stack that ARCHYTAS will develop to integrate and support those accelerators, as well as the simulation software needed for early prototyping of the full system and its components.
The growing complexity of applications combined with the need to execute them on resource-constrained platforms, demands highly efficient system-level optimization strategies. While advancements in hardware accelerators have improved performance, they remain insufficient without intelligent Resource Management (RM) that can dynamically adapt to the unique characteristics of both applications and hardware. Classical analytical models struggle to capture the intricate interactions in modern heterogeneous systems, prompting a shift toward machine learning (ML)-based RM approaches. This paper provides an in-depth analysis of the challenges and potential of applying ML to RM. We begin by presenting experimental examples that highlight the motivations for using ML and the challenges it presents. Two case studies - offline- and online-learning-based RM are discussed to illustrate the state-of-the-art approaches and their limitations. Finally, we outline the opportunities for future research directions to address open challenges and pave the way for efficient, adaptive, and reliable system-level optimization.
This paper introduces a high-precision, lowpower Bandgap Reference (BGR) circuit designed using UMC 28 nm CMOS technology. The proposed BGR circuit achieves a stable reference voltage of 0.647 V with a temperature coefficient of 17.69 ppm/degrees C across a temperature range of -40 degrees C to 125 degrees C. The utilization of advanced curvature compensation techniques involving subthreshold region MOSFET current, the design ensures minimal power consumption of 38.62 mu W. The optimized layout with 0.082 mm(2) area, minimizes parasitic effects and maintains robust signal integrity, making the circuit suitable for precision analog and low-voltage applications.
Assertion generation for Formal Verification (FV) needs an in-depth understanding of assertion language constructs, design fundamentals and RTL implementation techniques. Assertions are derived from a design’s natural language (NL) specification, but this is hindered by (i) NL ambiguity, leading to multiple interpretations, and (ii) the need to validate translations, as errors may occur. To address these issues, we propose LISA, an interactive framework leveraging large language models (LLMs), a formal verification tool, and human guidance. It systematically translates an NL specification into SystemVerilog Assertions (SVA) that accurately capture the intended behavior. LISA begins by breaking down complex NL descriptions into a structured verification plan using Chain-ofThought (CoT). It then generates SVAs for each item in the verification plan, formally verifies them using an FV tool, and analyzes statement coverage. For coverage gaps, LISA refines the assertions in an iterative feedback loop to enhance quality and correctness with the help of Retrieval Augmented Generation (RAG). We conduct a comprehensive LLM-assisted NL to SVA generation case study, producing syntactically correct SVAs with high statement coverage for the OpenTitan IPs, achieving 100% syntactic correctness with zero or one-shot prompting.
In recent years, in-memory computing has been extensively utilized for data-intensive applications due to its high speed and energy efficiency. Various memory technologies have been explored for this purpose, with Resistive Memory (RRAM) standing out due to its ability to naturally implement MultiplyAccumulate (MAC) operations, making it a promising solution for neural network acceleration. Additionally, RRAM is also applied in general logic computing applications. However, RRAM-based logic in-memory computing faces notable challenges, such as the need for repeated write operations, which leads to high latency and energy inefficiency. Furthermore, synthesized circuits often require mapping into large crossbars, reducing area efficiency. In this work, we introduce a novel logic in-memory computing framework designed to address these issues. Our proposed framework transforms the logic evaluation of AndInverter Graphs (AIGs) into MAC operations and binary step functions. This method eliminates the necessity for frequent write operations during the computing phase, thereby enhancing operational efficiency. Additionally, we propose two optimization techniques to achieve better area efficiency. Simulation results demonstrate that our proposed computing framework can perform logic evaluation without the need for writing during the computing phase. Furthermore, it achieves an average reduction of 86.13% in the Area-Latency-Product (ALP), a key metric for logic evaluation, compared to traditional designs.
