This paper presents a monolithic integrated circuit for temperature compensated biasing. The design is based on Gallium Nitride (GaN) high electron mobility transistors (HEMTs) on silicon (Si). The GaN process developed for this design currently provides only depletion-mode (D-mode) HEMTs. A proportional to absolute temperature voltage is created as well as a constant over temperature reference voltage, both are provided as output signals over a temperature range of -60 degrees C up to 250 degrees C. A temperature sensor is also integrated into the biasing circuit design, as an extra feature, with a sensitivity of 65mV/degrees C and a full scale linearity of 6.5%. The biasing circuit operates on a 24V supply voltage, with a direct current (DC) power consumption of 165mW.
Conventional computing architectures struggle to efficiently handle highly parallel models, such as Spiking Neural P (SNP) systems, due to the inherent limitations of von Neumann architectures. Existing software simulators for P systems cannot fully exploit their inherent parallelism, resulting in limited scalability and high computational overhead. To overcome these obstacles, this work proposes a novel hardware implementation of SNP systems using Resistive Random Access Memory (RRAM) technology. RRAM devices combine memory and processing capabilities, enabling non-volatile, analog, and threshold-based computation. By exploiting these features, we propose a hardware architecture that maps the behavior of SNP systems onto RRAMbased interconnected circuits. The presented implementation includes two key components: a spike counter subcircuit for the encoding of intercepting spikes in a neuron through the conductance states of RRAM devices and a rule assessment subcircuit that uses threshold switching for the evaluation and application of specific firing rules. Simulation results, based on the JART VCM RRAM model, confirm the correct operation of the proposed circuits, demonstrating their ability to efficiently simulate SNP system dynamics in hardware. This approach exploits the unique properties of RRAM technology and ultimately paves the way for real-time, bio-inspired computing applications beyond the limits of von Neumann systems.
This paper presents a quadrature VCO with an output frequency centered at 28 GHz, making it well-suited for 5G and 6G applications. A novel feedback technique utilizing the transistors' back-gate is proposed to couple the two VCOs. The core of the two LC-tuned QVCOs is optimized to achieve superior phase noise, making it highly suitable for mmWave frequency synthesizers. Developed in 22nm FDSOI technology, the proposed VCO operates from 27 GHz to 29.2 GHz, achieving a phase noise of -113 dBc/Hz at a 1MHz offset relative to the 28 GHz carrier frequency. It demonstrates an excellent FoM of -196 dBc/Hz and a tuning range of 8%, while consuming 4mW from a 0.8V supply.
Stochastic resonance (SR) can be defined as a phenomenon where the response of dynamical nonlinear systems to a weak input signal may be augmented due to the existance of noise tuned to the optimal level. Among others, the SR effect is quantified using measures as the signal-to-noise ratio, the output autocorrelation function, the residence time distribution, the input-output correlation function and mutual information. Here, the SR in a Chua electronic circuit, with its circuital elements designed to make it to operate in chaotic regime, and driven by unknown periodic signal and a Gaussian white noise is experimentally observed and qualitatively described by measures determined from DFT of switch-phase difference distribution. Among the improvements of this method we can highligh the following: it has an easy implementation, can be used in parallel processing and it doesn't require any prior knowledge or restriction of the input periodic signal. It also allows to calculate the optimal noise intensity for SR and decode amplitude modulated signals encoded in voltage impulses generated by switches between chaotic attractors.
In this study, a pure power-efficient analog hardware artificial neural network architecture is presented. The high-level architecture consists of circuits that operate in the subthreshold region, such as the sigmoid function circuit, Euclidean distance circuit, tunable current mirrors and a current comparator. The proposed artificial neural network is tested on a cuff-less blood pressure estimation classification task. The total power consumption is equal to 512nW and it achieves a mean accuracy of 95.1%. The proposed architecture is designed and tested employing the TSMC 90nm CMOS process, using the Cadence Virtuoso IC Suite for both schematic and layout design. To confirm the robustness of the proposed solution, both Monte Carlo and corner analysis are conducted. Additionally, postlayout results are contrasted with both software realizations and existing analog hardware solutions concerning power and efficiency.
In this paper, a low-power and rail-to-rail StrongARM comparator is proposed. A novel preamplifier stage which supports rail-to-rail common-mode input voltage (CMIV) is added to the conventional StrongARM. Furthermore, the proposed preamplifier also saves static power by using the existing clock gating and power gating from conventional StrongARM comparator. It saves 63.3% more power than state-of-the-art design. The resolution of the comparator is below 10 mu V and the CMIV varies from 0 V to V-DD. The design is scalable and ready to be used in data converters.
As the demand for higher speed telecommunications is growing faster and faster, telecommunications systems operating in higher frequencies are increasingly deployed. In this paper, a 5 G two-layered antenna with high-gain of 11.25 dB and ultra-wideband properties in the Ka-Band (bandwidth of 10 GHz, from 32.89 to 42.72 GHz) is proposed. This metamaterial antenna design is composed of a substrate and a superstrate, separated by an air gap, and a radiation element consisting of a central large patch, and a set of parasitic patches around it. The final design is the result of an optimization process, with the goal of achieving ultra-wideband properties, while maintaining the high-gain characteristic, in the 5 G Ka -Band. The Mountain Gazelle algorithm was used as an optimizer, due to its outstanding performance in latest research, as also confirmed from the optimal result produced in this research, which successfully operates from 32.89 to 42.72 GHz, while maintaining a high realized gain response, 11.25 dB.
This paper presents a hardware-accelerated polymorphic encryption framework for privacy-preserving machine learning. The approach employs a mode-switching polymorphic encryption scheme, enabling secure training and inference on data without decryption. We prototype a hardware-accelerated decision tree classifier that efficiently traverses encrypted data stored in FPGA BRAM, ensuring low-latency inference. Experimental results demonstrate the impact of encryption on classification accuracy and computational efficiency, providing a scalable solution for secure outsourced machine learning training.
Frequency selective surfaces have been utilized in smart electromagnetic environments due to their diverse range of applications. The geometric configuration of these periodic structures can enable them to be used for reflectivity, absorption, or transmission of electromagnetic waves. In this work, we exploit their reflectivity in the Wi-Fi frequency bands (2.4 GHz, 5 GHz, and 6 GHz) and transmission in 5G NR FR1 n78, 3.3 - 3.8 GHz. A novel nature-inspired metaheuristic algorithm, i.e., the African Vultures optimization algorithm, has been assessed and exhibited satisfactory results in unimodal and multimodal functions. As a result, it is utilized as a promising candidate to optimize the geometry of the proposed surface. Numerical results demonstrate the effectiveness of the proposed approach in enhancing electromagnetic performance, validating its potential for real-world applications.
Many dc supply and bias voltages are needed in heterogeneous phased array systems, due to the high component count. We present a low-cost versatile power management unit for the supply of such a system. From a single dc input voltage it generates six fixed voltage levels, four adjustable low-voltage bias voltages, two adjustable negative bias voltages, and two adjustable high-voltage outputs. The adjustable voltages are controllable via SPI communication, for which a Teensy microcontroller was used in combination with Matlab to create a simple to use graphical user interface. Furthermore, to cater to the needs of gallium nitride (GaN) power amplifiers, a protection circuit is added to ensure that the high-voltage outputs can only be switched on as long as a negative bias output is present.
System identification plays a crucial role in engineering and many other scientific fields, yet comparative evaluations of identification methods remain limited. Many existing approaches assess model performance primarily through one-step-ahead prediction accuracy. While convenient, this metric alone does not adequately determine whether a model truly captures the system dynamics. To address this limitation, we propose a standardized evaluation framework that incorporates the accuracy of horizon prediction. Additionally, our framework highlights the importance of sufficient excitation spectrum in training data. A model trained on data with a narrow excitation range or using identification techniques with poor generalization capabilities may struggle with new input dynamics, even if the training dataset is large. Our open-source framework offers a comprehensive training and evaluation strategy, facilitating both research advancements and practical applications in system identification.
This paper proposes a Single-Inductor Multiple Output (SIMO) DC-DC converter based on a hybrid topology, which effectively enhances the system's transient response speed and reduces the cross-regulation between channels through an innovative control strategy. The proposed converter combines charge control mode with valley current adaptive conduction time control mode. It cascades Low Dropout Regulators (LDOs) with high Power Supply Rejection Ratio (PSRR) to suppress interchannel cross-regulation. Meanwhile, the adaptive conduction time control mode improves the dynamic performance of the converter across a wide load range. The proposed converter is verified using the 250 nm BCD process, achieving a peak efficiency of 93.5 %.
D-band power amplifiers (PAs) are critical components for 6G communications. While unconditional stability in the frequency band of interest is regularly taken into account in the design process, the stability at lower frequencies are also required to be evaluated to avoid possible oscillation problems. In this paper, we propose a power amplifier in D-band stabilized from DC to f(max) in simulation by introducing custom inductors at the gate terminals of the pseudodifferential stage with cross-coupled neutralization capacitance, C-N. The design methodology of the PA and the implementation of the inductors are comprehensively discussed. By cascading four stages with transformer matching networks, the PA achieves a gain of 16.2 dB, 8 dBm of saturated output power, and an OP1dB of 3.6 dBm.
This study introduces a unique memristor emulation unit (MEU) that functions without any DC bias and consumes zero standby power, incorporating an inverse frequency response. The architecture comprises an n-type Dynamic Threshold MOSFET (DTMOS), an n-type MOSFET, and a tunable capacitor, allowing it to support both incremental and decremental memory behaviors. It operates effectively in both floating and grounded configurations up to 50 MHz, achieving a memristance range from approximately 33 k Omega to 33 M Omega. The CMOS layout occupies a chip area of about 62.93 mu m(2). The proposed MEU also shows strong resilience against noise and process variations, and its practical feasibility has been confirmed through experimental implementation using an ALD1116 MOSFET array and a UA741 operational amplifier.
This research work provides a measurement-backed analysis of a single-ended chip-to-chip bondwire interface (BWI) with a signal pattern of ground-signal-ground (GSG) designed for minimum insertion loss. Different approaches to reducing the bondwire length and signal disturbing factors at the intersection of two microchips (such as the scribe lines and sealrings) are investigated and compared. Reproducible, seamless measurements from DC to 330 GHz have successfully demonstrated that GSG bondwire interconnects with only 3 dB insertion loss at 300 GHz can be realized without the need for tailored on-chip structures, which are typically area-intensive and can significantly limit the bandwidth and universal applicability of the chip.
Digital horticulture is the integration of digital technologies into horticultural practices to optimize production, improve efficiency, and promote sustainability. In this work we provide guidance on how to build a user-friendly and low-cost digital horticulture system with off-the-shelf components aimed at operating inside a greenhouse.
Probabilistic computing has emerged as a promising paradigm to tackle computational challenges in artificial intelligence (AI), machine learning (ML), and optimization tasks. Unlike deterministic computing, it leverages controlled randomness to enhance efficiency and scalability. This paper explores the integration of probabilistic bits ($p$-bits) within magnetic tunnel junction (MTJ) devices, utilizing their inherent stochastic switching behavior to implement probabilistic computing architectures. It demonstrates how MTJs enable energy-efficient, hardware-compatible solutions by eliminating the need for complex pseudo-random number generators. A crossbar-based p-bit array is proposed, incorporating a digital-to-analog converter (DAC) and a sense amplifier (SA) to facilitate probabilistic operations. This work highlights MTJbased probabilistic computing as a viable alternative for future low-power, high-performance AI accelerators.
This paper presents a novel, low-cost approach for establishing a platelet-rich plasma (PRP) facility that integrates affordable Raman spectroscopy with advanced machine learning techniques for automated cardiovascular disease diagnosis. By reviewing cost-effective PRP production protocols, we demonstrate that high-quality PRP can be prepared using standard laboratory equipment at significantly reduced costs, bringing the per-session expenses below USD5. Furthermore, by incorporating a low-cost Raman spectrometer ranging from USD3,000-USD3,800 into the facility, real-time analysis of PRP samples is enabled. Surface-enhanced Raman spectroscopy (SERS) data of platelets are processed with deep learning algorithms to detect subtle biomarkers associated with cardiovascular pathology. Experimental evaluation revealed that the utilized deep learning models achieved consistently high 100 percent test accuracy under optimal training conditions, thereby validating the system's reliability and potential for early, automated cardiovascular diagnosis along with other PRP-related procedures. The preliminary results indicate that this integrated infrastructure holds significant promise for early, automated cardiovascular screening while maintaining overall low-cost operations.
The increasing integration of wind energy necessitates robust fault management strategies to enhance grid stability. This paper proposes a multistep bridge-type FCL with dynamic impedance regulation to improve transient stability in DFIG-based wind turbines. The proposed FCL effectively limits fault currents, stabilizes DC-link voltage, and minimizes torque and power oscillations. Simulation results confirm that the proposed FCL outperforms conventional solutions, including the SDBR and BFCL, by achieving superior fault suppression and system recovery. The stepwise impedance control reduces switching losses, component stress, and electromagnetic interference, ensuring a cost-effective and practical implementation. Future work will focus on experimental validation and large-scale integration.
This report presents a stability analysis of a synchronous boost DC-DC converter, performed using LTSpice - a software platform for simulation of analog electronic circuits. The purpose of the study is to evaluate the behavior and stability of the converter in different operating modes, by analyzing the frequency response of the feedback. The amplitude and phase margins, which serve as the main indicators of the stability of the system, were calculated using $A C$ analysis. The report examines the influence of the regulator parameters, filtering components and load conditions on the dynamic response of the circuit. The presented simulation results demonstrate the importance of precise design of the regulator loop and confirm the effectiveness of LTSpice as a tool for preliminary verification and optimization of power systems. A major advantage of using LTSpice is the ability to implement an additional way to analyze the power circuit of a synchronous buck converter. The analysis supports a better understanding of the principles of stable operation of DC-DC converters, which is essential for the modern electronics and could reduce losses in the circuit.
