This paper demonstrates a 26.5-GHz 2-D Butler matrix based 4×2 array switched beamformer. By using a 2-D Butler matrix, feed lines between IC and antennas are uniform, which is a critical problem in an integrated Butler matrix for a 1- D array since it requires complex phase matched routing on PCB. A proposed switched beamformer consists of a signal distribution IC and two switched beamformer ICs. Reconfigurable switches with a function of power divider/combiner are integrated for additional beam patterns. The proposed switched beamformer can generate total 22 beams, which cover a whole scan angle with a low gain variation. Measured beam patterns show that the proposed switched beamformer can cover any 3-D spatial angle of ±44° in azimuth and ±43° in elevation even with a low spatial beam resolution. To our knowledge, this is the first 2-D array switched beamformer based on the Butler matrix in millimeter wave bands.
In this work we propose a new architecture for a wideband phase shifter, based on upconversion and downconversion of the wideband input signal using phase-shifted mm-wave local oscillator (LO) signals. Phase shifting of the LO at a single frequency is achieved using an on-chip quadrature voltage-controlled oscillator (QVCO) and vector modulation (VM). The issue of mixer image band phase shift interference is mitigated using filtering at the mm-wave intermediate frequency (IF). The concept is demonstrated in 65nm CMOS in the design of a 6–22 GHz full 360° phase shifter using a 84 GHz LO and 62–78 GHz IF range. The phase shifter achieves phase error <1.05° and amplitude error <0.2 dB for 7-bit resolution with power consumption of 137 mW (including buffers) and core area of 0.26 mm 2 .
A 0.324-THz multiplier-based (x16) transmitter with an on-chip patch antenna has been implemented in a 130-nm SiGe:C BiCMOS technology with an $f_{\mathrm{T}}/f_{\mathrm{m}m}$ of 350/450 GHz. Power management and biasing are integrated on-chip for post-silicon optimizations of output power and de-to-THz efficiency. Each circuit block can be programmed over a serial peripheral interface for bias current. Three individually programmable low-dropout voltage regulators supply the x8 20-to-160-GHz multiplier chain, the two-stage 160-GHz power amplifier, and the 0.32-THz frequency doubler, respectively. Measurements after optimization reveal a dc-to-THz efficiency of 2.65% with an output power of 6.6 dBm and a dc power consumption of 170 mW operating at 0.324 THz.
A 140GHz 4-element RF beamforming phased-array receiver (RX) has been demonstrated in 22nm FDSOI CMOS. The proposed single-side-band architecture provides >25dB and >20dB measured image rejection ratio (IRR) across 4GHz and 8GHz channel bandwidth centered at 7GHz intermediate frequency (IF). Each front-end element consists of a wideband low-noise amplifier (LNA) and a vector-modulator phase shifter. The 4 elements are combined on chip through power combiners and driver amplifiers before the double-balanced mixer, which is driven by an on-chip multiplier (x9). The receiver consumes 480mW DC power and provides <10dB noise figure from 135 to 147 GHz. The RX is measured up to 32 and 24Gb/ $s$ in the probe and over-the-air test. To the authors' knowledge, this CMOS RF beamforming RX presents the largest channel bandwidth (8GHz) with 20dB IRRmin at low IF consuming the lowest DC power per element (120mW) among the published phased-array RX in the 140GHz band.
A frequency quadrupler based on cascaded push-push frequency doublers is presented in this work. Push-push frequency doublers suffer from limited power efficiency and conversion gain, mainly due to second-harmonic feedback. Conventional harmonic reflectors minimize this undesired feedback introducing a common-mode second-harmonic resonance, at the price of increased area and reduced bandwidth. In this design the harmonic reflector is embedded into the input matching network, resulting in a more compact design. The coupling coefficient between the multiple windings of the transformer secondary is used to decouple the differential-mode inductance from the common-mode inductance, that acts as a wideband harmonic reflector. A common-gate transistor is stacked with the push-push pair to further boost the output power while reusing the same current. Two push-push frequency doublers are cascaded without additional power amplification stages. The quadrupler, implemented in 28nm CMOS, achieves a peak output power of 0 dBm and peak power efficiency of 50% at 77 GHz and the 3-dB bandwidth is from 70 to 86 GHz.
