This research provided the latest development of sintered silver (Ag) and copper (Cu) as die-attach materials based on the patent data retrieved from www.lens.org using the two criteria of patent claims of “silver” or “copper”, “sinter*” and cooperative patent classification (CPC) of H01L2224/8384 (die-attach application with sintering technique). Based on these two criteria, the patent filing trend of sintered Cu mirrored those of sintered Ag, including the peak in 2015. Closer data inspection revealed that this mirroring reflected the patent claims technique, which included Cu and Ag, and sometimes other elements, such as gold, nickel, palladium, aluminium and platinum, as metal particles to be sintered for die-bonding applications. At the same time, patents that claimed either the Cu or Ag exclusively for their paste formulation or used these sintered joints as part of the microelectronic packaging designs, were also available, but generally restricted to sintered Ag joints. However, the obviousness or “equivalences” between sintered Cu and Ag in the patent prosecution process might pose a problem in patent infringement cases, but none had been reported. In addition, other “valuable” patents based on patent family size and forward-citations counts, were also identified and discussed in developing these sintered metal technologies. In conclusion, the rapid development of sintered Ag and Cu as die-attach joints in the microelectronic packaging industry, especially among power module manufacturers, had matured in their technology life-cycle, based on the patent filing data.
In conventional semiconductor machine operation method, it is required the operator physically to be in front of the machine. The operator needs to walk from one machine to another machine just to make the machine run. Without operator, the machine cannot run smoothly especially if there are many machine stoppages. Because of this issue, the engineer needs to work on how to reduce the machine stoppages and improve the machine performance. In certain circumstances, the machine has a limitation, and the machine stoppages cannot be improved anymore especially to the old machine generation. To maintain the old machine generation performance is very challenging and sometime the machine spare part is also obsoleted. By introducing the remote system in the semiconductor, it will help to solve the machine limitation issue. From the control room, the operator able to clear the machine stoppages without physically need to be in front of the machine. It will help to reduce operator workload, reduce the machine downtime, improve the man-to-machine ratio and at the end reduce the cost. Fig. 1 below shown the comparison between with and without remote system. The number of operators can be reduced significantly, and the movement of the operator also can be reduced. Bear in mind, not all the machine stoppages can be remoted. The remote system also has its own limitation. For example, change material, change lot, and change the machine part cannot be done remotely. Its still require operator physically to be in front of the machine.
Ultra-fine SAC305 solder is widely used as lead-free interconnection in advanced packaging because of its advantages such as good joint strength, thermo-mechanical fatigue behavior and creep resistance. Stencil printing remains the technology of choice for assembling because of its ease of process control, flexibility of usage, wider process window, and economic usage. Advanced package involves integration of different components, copper (Cu) pillar, flip-chip devices, and chips in one package to achieve multiple functions in one system. The need to accommodate ever increasing demands for reduced footprints requires constant inventions of flip chips with Cu pillar diameter of $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ and smaller. Many mobile communications consist of 6 or more flip chips in a single package. Conventional flip-chip attach uses flux and Cu pillar solder cap for interconnect formation, it is a challenge to print solder paste of fine geometries below $\mathbf{70}\boldsymbol{\mu} \mathbf{m}$ . Heraeus's solder paste makes use of ultra-fine spherical shaped solder powder (T7 particles size) to create strong metal coalescence for bonding during reflow process of Cu pillars onto substrates. Reduction in flip-chip Cu pillar diameter to $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ requires further reduction in stencil opening to $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ , thus limiting the usage of T7 paste. Present study reports stencil printing application of new version of T7 solder paste with reformulated flux system. The application evaluations using $\mathbf{55}\boldsymbol{\mu} \mathbf{m}$ stencil opening (SO) revealed good results by successfully printing $\mathbf{35}\boldsymbol{\mu} \mathbf{m}$ line spacing (LS) without defects such as bridging, missing & inconsistent dots. It also achieved average paste release volume of ~30% up to 12hours of continues printing.
This paper reports on the advanced assembly technology for small chip size of Fan-out WLP(FO-WLP) using high expansion tape. In a preceding paper, we reported that we have developed new tape expansion machine which can expand tape in four directions individually. Using this expansion machine device, we have developed high expansion tape which can get enough chip distance after expansion. Our expansion technology provides both high throughput and high placement accuracy. These previous studies have been evaluated using 3 mm x 3 mm chips assuming an actual FO-WLP device. Since our process can be handled by wafer size, smaller chip size improves throughput than larger chip size. In this study, we evaluate with 0.6 mm x 0.3 mm chip size and investigate tape characteristics required for small chip size expansion. By optimizing adhesive thickness and composition of adhesive, we succeed in developing high expansion tape for small chip size with good expandability and no adhesive residue on the expanded chip. We indicate that our proposal process is also effective for small chip size of FO-WLP.
The major technology shift on the horizon to 5G, autonomous vehicle, and AI have driven semiconductor industries to strive for the continuous development of electronic devices with better functionality and higher power efficiency. Ultra wafer thinning process appears to be one of the promising solutions to produce semiconductor chip with lower resistance and hence better electrical performance. Apart from electrical performance, it is very important to understand the mechanical properties of the ultra-thinned silicon chip. Different wafer back-grinding, stress relief etching and metallization steps in wafer thinning process flow will determine the die strength, surface condition, and reliability of the semiconductor chip. When wafer becomes thinner, it becomes more susceptible towards stress induced failures such as wafer saw chipping and die crack during assembly process. Also, a correlation is found between the wafer back metal surface roughness and solder die attach performance. In this study, wafers were processed with several ultra-thinning process flow that involves different etching method and metallization. The mechanical and surface properties of the wafers were then characterized to identify the correlation between the resulted properties and thinning process flow. In order to enhance the reliability and robustness of the final semiconductor package, it is very crucial to understand the effect of wafer back metal thickness and surface roughness of ultra-thin wafer towards backend assembly processes.
Corrosion of electronic packages remains a significant threat to microelectronic circuits. It affects the reliability and lifetime significantly. In the past few years, knowledge acquired in this field is a high amount of copper sulphate in the Copper-Argentum (Cu-Ag bimetallic) system that induces copper wire corrosion. The paper aims to determine the potential factors that can reduce copper sulphate generation at the Cu-Ag bimetallic system and optimize the elements toward a minimal amount of copper sulphate by the simulation response. The motivation is to build the risk margin model through the design of experiment replication. The factors study MSA concentration, Methane sulfonic acid (MSA) volume and the baking temperature. The aim is to elucidate the effectiveness of post-bake toward preventing package corrosion in semiconductor packages. The methodological approach is the design of the experiment and analyses the atomic percentage of copper sulphate through X-ray photoelectron spectroscopy (XPS) scanning. Three factors for the design of the experiment are the baking temperature, MSA concentration and MSA volume. For example, increasing the baking temperature will reduce the package's MSA ionic content, resulting in a lower atomic percentage of CuSO4.
The presence of foreign metal particle inside the encapsulation of IC package can seriously cause a near short failure mechanism. The near short will be degraded to an intermittent contact and finally a permanent short at the early life. Therefore, it is essential to have the right failure analysis tools, equipment, and methodology to detect the presence of particle inside package. It would not be an issue if metallic particle found inside package as there is already X-ray equipment that can be used to detect this element. However, if the particle is either low density and/or non-metallic material, then the risk will be very high. In failure analysis, the success rate of finding the root-cause of the failure is very much associated to the right FA methodology approach used to precisely detect the presence of particle inside package. The risk will be higher if the current FA tools or methodology is not able to detect this particle. In this paper, the low density and non-metallic particle that will be studied is Carbon particle. Objective of this paper is to identify the most suitable and FAST failure analysis method for this carbon black particle detection. The approach used was package fault isolation using a combination of laser decapsulation and electrical micro-probing with a curve tracer. EDX elemental analysis will be also carried out as an auxiliary technique to confirm the properties of the element. Based on the evaluation results, the combination of laser decapsulation and electrical micro-probing with curve tracer are two essential techniques that can be used to locate the presence of this carbon black particle. These two techniques have been used as part of package fault isolation methodology. This technique can also be extended to other low density and non-metallic type of particle such as Aluminum. These new techniques have been embedded as part of the failure analysis flow with a detailed logical flow of a series of non-destructive steps to fault isolate the failure, followed by a series of destructive tests to understand the nature of failure mechanism and finally, EDX technique to characterize the elements of the particle. These new techniques have helped to speed the time to premium results while also opening new synergies among other instrumentation in the FA laboratory.
A System in Package (SiP) module development including Surface-Mount Technology (SMT) and Flip Chip (FC) for the passive components and controllers placement on direct Au substrate. In addition, the Laterally Diffused Metal-Oxide-Semiconductors (LDMOS) and GaN dies are also placed by die attach process. An investigation was conducted to analyze the root cause of the low peel strength on this Au stitch bond to Au pad structure. In this investigation, a low peel strength mechanism of Au wire bonding on direct Au substrate was demonstrated. The interdiffusion behavior of Cu and Au was analyzed by a Transmission Electron Microscope (TEM) with simulated heat treatment condition. In order to validate the root cause, the fracture mode was investigated and its corresponding pad surface analysis was performed by Auger Electron Spectroscopy (AES) analysis on the most surface through a step-by-step method from substrate incoming until wire bond completed. The results indicate that the low peel strength was caused by the poor adhesion between Au wire and Au pad, fracture occurred at wire and pad interface. With a deep dive analysis by AES in comparison with pure and processed Au pad surface, the results indicate the pad was contaminated by Cu migrated from base and its oxide caused degradation of adhesion of Au wire to Au pad.
Sidewall crack is the common defects mode in the mechanical wafer dicing process. Most challenging is adaption on the old wafer technology with the high density of metallization TEG along the sawing street & blade condition. A critical factor to be considered in the mechanical wafer dicing is the blade condition (Clogging, Loading) during cutting. High density of metallization Test Element Group (TEG) causing mechanical stress to induce, due to blade blunt. On wafer dicing process new methodology explored to deal with challenges encountered. In order, to ensure blade in the good condition; cutting sequence method should be considered. On this technical paper, methodology of cutting sequence was optimized to increase cooling system (water flow) was demonstrated. The combination of the cutting sequence and Z1 shower flow setting resulted the good improvement of sidewall crack at PSSO testing gate from 8 percent to 3 percent reduction.
Demand for higher levels of integration with cost effective solution have driven the increased use of and innovation in System in Package module for Radio Frequency (RF) new products. System in Package (SiP) module high integration capability allows for wide range of power and frequency applications ranging from low power remote heads to massive Multiple-Input Multiple-Output (MIMO) systems. System in Package module employs both active devices and passive components, such as inductor, capacitor and resistor, together with other materials like substrate, solder and gold wire. This paper discusses the characterization study of solder extrusion during the development work for a new product employing new substrate plating. The study covered two characterization activities on key factors affecting solder extrusion under inductors namely, material characterization and process characterization. Materials characterization covered the study of new substrate plating and the inductor type considered under the new product which may impact solder extrusion. Process Characterization covered the study of solder paste screen print process versus their solder extrusion output response. Characterizations resulted to the definition of optimum pre-mould plasma cleaning parameter and solder screen printing process parameters for the new product, the results of which were integrated in its further development, qualification and production release.
Finite element (FE) method has been widely used for package level and board level reliability predictions. Recently, there are more components packaged in single unit and complicated geometry combining with finer mesh should be built in FE model. To simplify model building procedure and reduce modeling time, FE model is often separated into two or more parts with discontinuous mesh, which are package and solder joint with a printed circuit board (PCB). By using Multipoint constraints (MPC) method, the degree of freedom (DOF) will be constrained and transmitted between fine and coarse mesh. This simplified FE method usually induces some numerical errors. To balance efficiency and accuracy, two geometric parameters, constraint location and mesh size ratio between package and solder joint, will be discussed in this paper. The results show that setting the constraint layer farther from the solder will get lower error percentage. Furthermore, constraint location, at interface of two substrate layers or at inner of single material, isn't a significant factor. In mesh size discussion, a finer mesh usually gets a more accurate solution until it converged. From this study, an appropriate meshed size ratio, P/S ratio, is proposed for getting the converged result in reasonable time. In addition, two Pb-free alloys, LF35 and SACQ, are compared as well since the discrepancies of material properties lead to varying degrees of numerical error.
Ball grid array (BGA) package is widely used in electronic packaging. This type of package can accommodate high I/O in the small form factor package size compared to the quad-flat package (QFP) and quad-flat no-lead (QFN). Due to its function to electrically connect the package substrate to the printed circuit board (PCB), it is important to ensure the 2 nd level interconnect is reliable against cyclic thermo-mechanical load. Ever-increasing functional density in microelectronic components requires a continuous redesign of packaging technology. Characteristic attributes are form factor, pin count, pitch, power density, diverse application and harsh environment. Packaging engineers have to ensure new product designs will act according to specifications and will survive in the field for the targeted market. The interconnection of the semiconductor package and PCB is one of the most critical elements in the electronic control unit. A thermal mismatch between component and PCB, together with varying temperatures causes cyclic deformation and fatigue of solder interconnect. The semiconductor manufacturers apply an accelerated temperature cycling test to assess the risk for early failure in the field. To reduce the development cycle, NXP is applying virtual prototyping and testing by simulation. This allows to run extensive design studies in a relatively short time with only a few prototype builds for empirical validation. NXP has established robust simulation technics for the assessment of fatigue in solder alloys. In this paper, we want to share a design study for BGA. We will derive the significance of various design parameters concerning the solder joint reliability in a board assembly. For instance, we will assess the influence of PCB pad diameter, solder stand-off height, solder alloy materials, die sizes and package core thickness. The simulations described in this paper are done during the early design stage to ensure all NXP products are robust and reliable. To evaluate the relative failure risk between design cases, a volume average approach on the accumulated creep energy density is used. We will discuss the significance of mentioned design parameters with respect to the board-level reliability test conditions. We will provide, a few guidelines from a mechanical standpoint to mitigate solder joint bulk fatigue under board level temperature cycling (BLTC) test conditions.
Intel's Client Computing Group's (CCG) project Athena is generating a new wave of exciting Evo brand notebook systems. Project Athena has enabled foldable display systems as a new device category. To influence the industry towards this new device category and technology readiness proof point, CCG has developed a foldable display notebook system called Horseshoe Bend. Horseshoe Bend uses a 17.3-inch foldable OLED display that's being enabled by Intel. This paper discusses the Horseshoe Bend system design challenges, innovations required, and solutions implemented. In general, foldable systems need to support usages of multiple form factors into one physical system- 17.3-inch tabletop All-in-one system, and 12.5-inch notebook when folded in laptop posture. This poses multiple challenges- support orthogonal requirements and resolve foldable display system integration issues. This paper details how this system design solved issues of display displacement absorption to integrate into system chassis, higher performance expectation, orthogonal requirements of input/output (I/O) support, new audio and imaging usages, innovations in printed circuit board (PCB) design, among others.
Cu2ZnSnS4 (CZTS) thin films were fabricated using high power impulse magnetron sputtering (HiPIMS) method and their chemical composition, surface morphology, and it's resistivity were investigated. Tools such as energy-dispersive X-ray spectroscopy (EDX), X-ray powder diffraction (XRD), field-emission scanning electron microscopy (FESEM), and atomic force microscopy (AFM) were used to analyze the CZTS thin films. AFM was used to investigate the shape and roughness of the film's surface. EDX was used to analyse the chemical compositions of the prepared samples, and the films demonstrated the non-stoichiometry of CZTS. The thickness of CZTS film was determined using surface profiler and cross-sectional image. The results of XRD pattern revealed the (112), (220), and (312) CZTS peaks. The development of a quaternary Cu2ZnSnS4 phase with a high preferred orientation along the (112) plane is confirmed by this experiments.
The continued drive for digitization is making our everyday experiences to be greatly interwoven with sensing devices. Sensors are nowadays embedded seamlessly in our various daily activities and interconnected together through a network. Different types of sensors are today well ingrained in our life, some sensing changes in environment such as temperature or pressure, some sensing dynamic movements such as acceleration others sensing physical quantities such as magnetic fields in piezoresistive sensors or light for proximity purpose. Various kinds of sensing technologies exist: Micro-electromechanical systems (MEMS) [1] sensors, Optical sensors, Hall sensors. When packaging these type of sensors, regardless of their different operating principles one common aspect converges for all of them: the package housing needs to be designed in such a way to reduce stress transmissions to their sensitive parts. Failure to do so will result in unwanted drifts influencing the sensor final output and hence its performance. When stress is high enough it will result in unwanted deformations leading to a shift. As thermomechanical modeling engineers, and in collaboration with package design, in our strive of Design for X (DFX), we must identify and propose packaging solutions that lead to thermomechanical stability in such a way that our final device is as flat as possible and/or the sensitive parts are well decoupled from the remainder of the plastic package such that thermomechanically induced stresses are eliminated or reduced to a minimum. In addition to this, the thermo-mechanical modeling engineer, needs to ensure that in the strive for DFX, all thermo-mechanical aspects and potential detractors are bottomed down including but not limited to Design for Reliability (DfR) and Design for Manufacturability (DfM) [2], [3]. While this paper will not go into specific details of the latter it is fundamental for the thermo-mechanical expert to ensure a holistic approach in the recommendations made. It is also understood that in a thermo-mechanically stable structure, a device is expected to benefit in various ways including in reliability, in its operational performance and during manufacturing.
Drop test durability has been a major concern for devices widely used in mobile applications. JEDEC standard is introduced to characterize IC package drop performance such that a consumer product manufacturer could have a readily available benchmark to assess reliability of components from different suppliers under the same test conditions. At first explicit solvers were extensively used to tackle the free fall problem due to its transient and dynamic nature. They were soon simplified to Input-G method to avoid complexity in modeling contact event. Still their inherent poor numerical stability during simulation has limited its application to drop events with small to medium size unless the analysis utilizes very fine time incremental steps, which, in turn, is time consuming. In addition, many component suppliers usually do not have such software. Therefore, implicit solver has recently been employed to simulate board level drop test. Its limitation lies with its connate incompatibility with the direct application of the base acceleration profile but can be overcome by additional treatment of the boundary conditions. This paper investigates the simulation methodologies of JEDEC board level drop test using implicit solver. It demonstrates that both Direct Acceleration Input (DAI) method and Large Mass Method (LMM) could be used to model the current industrial specified drop test, which is a moderate transient process, but the latter is a better option as it captures the real response of the package assembly under test. Actual drop tests were carried out and compared with simulation predictions, they are found in good agreement. Further examination of the current common industrial practice raises concerns about the accuracy of its data collection and interpretation of JEDEC board level drop test results. Possible solutions are offered for improvement of board design and data analysis.
In the era of electrification and automatization, semiconductor chipmakers constantly evolve to produce a performance-edge-over package in several respects: Higher operating temperature and voltage. To enable such requirements, automotive electronic designers must consider delamination robust packaging solution to support the die technology. In this paper, 2 case studies at molding process are used to prove fast and high accuracy method to achieve first time right mold tool design that worked in equilibrium with process, material and leadframe design. The aim of this paper is to prove the use of simulation method to support tool designing during initial risk assessment input, considering that resolving moldability problems is a time intensive process. This paper outlines a systematic approach using simulation to predict risk and improves design for new mold tools. The first case study is on Clip Flat Power package (CFP) with 2 sided package body that has been encountering incomplete fill on die types smaller than 1mm2 size. By using short shot analysis data that indicates unbalanced mold flow between top and bottom package, the mechanism of flow has generated idea to investigate the ideal opening, depth, location of gate with respect to package construction. With the computer aided simulation, proof of concept (PoC) is executed. The 3 factors were varied and filling percentage is used as output response to gauge performance of various legs. The study showed location of the gate is a key factor to achieve balanced flow, hence the ideal position of the gate is predicted. The actual tool able to eliminate incomplete fill on packages with die smaller than 1mm2 size. The study also proved that 2 sided package body with clip interconnects need to achieve minimal difference between top & bottom mold flow to prevent incomplete fill phenomena. The second case study is on small outline CFP with open heatsink where molded units in strip form can trigger delamination at time 0 due to poor precision degating process. Poor punching mechanism can lead to package delamination. Simulation model of molded strip is subjected to various factors; 1) Precision degate tool (PDT) to package body distance, 2) Precision degate tool design. The study shows angular punch tool is most effective factor among all others and able to reduce delamination. Further study is to explore construction of predictive model that can estimate risk of heatsink flash on open heatsink CFPs using high fluidity EMC. The objective is to promote application of simulation on tool, design for manufacturability and enable faster time to market.
Durafuse™ HT—a novel high-temperature lead-free (HTLF) solder paste design, combining two constituent powders has been developed as a drop-in solution to replace the high-Pb solder pastes in power discrete applications. In the design, the rigid high-temperature SnSb-based powder maintains the high-temperature mechanical performance and the ductile Sn-rich powder lower the reflow temperature to be comparable to the high-Pb. HTLF-1, one of the HTLF solder pastes with relatively lower Sn-rich phase, maintained bond shear strength up to 15MPa, even around 295°C. Another solder paste, HTLF-2, having relatively-higher Sn-rich phase, had the comparable bond shear strength to Pb92.5/Sn5/Ag2.5, around 295°C, but exceeded substantially below 250°C. The encapsulated discrete components were successfully built with both HTLF solder pastes using the existing high-Pb process, which includes the paste deposit, die & clip placement, residue cleaning, molding & curing etc. It demonstrated the drop-in processing compatibility. Those components had successfully gone through the traditional product qualification tests, namely the pre-conditioning, the moisture sensitivity level 1 (MSL-1) and 1000 cycles of TCT (−55/175°C). Both HTLF solder pastes had the superior RDS(on) comparing to Pb92.5/Sn5/Ag2.5 before and after 1,000 cycles TCT (−55/175°C). The intrinsic lower electrical resistivity of Sn was attributed to superior electrical performance.
The rapid development of Thermal Conductive Adhesive (TCA) by using highly thermal conductive fillers like graphene nanoplatelets (GNPs) and boron nitride (BN) has heightened the need to hybridise both fillers in order to improve the thermal, mechanical and water resistance properties of the adhesive. The hybrid composites were prepared by varying the GNPs sizes, ratios, and silane coupling agent. The result indicates that hybrid GNPs15/fBN_KH560 composites exhibit the highest thermal conductivity (1.159 ± 0.02 W /mK) at a GNPs ratio of 0.75 compared to other composites. However, shear strength analysis shows a contradicting result where hybrid GNPs5 composites show a higher result than hybrid GNPs15 composites at all GNPs ratios. The difference is due to the size of the GNPs filler, where bigger fillers are preferable to transfer heat due to lower filler-polymer resistance, while smaller fillers are required to transfer stress due to the high effective surface area of the filler-polymer. The moisture analysis shows that hybrid GNPs15 composites absorb more water than the hybrid GNPs5 composite due to the lower filler loading and the wrinkling of GNPs15 filler that hinder its ability as a barrier against water. Consequently, the shear strength of hybrid GNPs15 composites is lower than hybrid GNPs5 composites for all GNPs ratios. It is also worth noting that the thermal and mechanical properties of hybrid composites containing fBN at all GNPs ratios are better than unmodified BN due to the well-dispersed filler, as depicted in the microstructure analysis.
With the rise of dark silicon, liquid cooling has become essential for high-performance integrated circuits, like central processing units (CPUs), to support continuous and reliable operations. The state-of-the-art liquid cooling designs commonly adopt quasi-steady coolant flow rate and suffer deteriorating cooling efficiency as the thermal boundary layer develops. This work introduces an intermittent jet and surface structure co-design approach for electronics cooling, and demonstrates the enhancement of cooling performance by both numerical simulation and experimental measurement. The proposed co-design approach is evaluated based on a commercial CPU liquid cooler. The coolant flow rate is controlled to follow a trapezoidal waveform, and the heat sink surface is manufactured with cylindrical grooves. The numerical results show that the flow intermittency continually disrupts the growth of thermal boundary layer and promotes secondary motion of cavity vortices, leading to a reduction of the overall thermal resistance up to 35%. The cooling performance is consistently improved as the duty cycle decreases and the intermittency frequency increases. This tendency is confirmed by experimental results conducted at the same intermittency conditions and heat sink geometries.
