• 学术搜索
  • 科研智能体
    • Research Labs
    • AI 阅读
    • AI 文库
    • 深度研究
    • 学者亮点
  • 学术资源
    • AI2000
    • 期刊/会议
    • 学者库
    • 学术API
    • 溯源树
    • 数据集
  • 知识沉淀
    • 学术空间
订阅小程序
旧版功能
aminer vip
开通会员低至0.73元/天
一次搞定AI科研
立即登录
  • English
  • 联系方式
    Asia Pacific Conference on Circuits and Systems

    Asia Pacific Conference on Circuits and Systems

    Conference

    年发文量

    研究主题

    论文(3157)

    排序
    1A 66.7Db-Sndr Pipelined-SAR ADC with On-Chip Bit-Weight Calibration Achieving ΔSNDR < 2.4 Db Across PVT Variations
    Jinwei Zhang, Haolin Han, Ruili Ren,Shubin Liu,Zhangming Zhu

    This paper presents a two-stage pipelined-SAR ADC with offset cancellation technique, which cancels the equivalent offset induced by the comparator and residue amplifier (RA) by forming a feedback path with a notch filter and level-shift circuits. Moreover, the ADC is calibrated on chip through one-time bit-weight calibration together with an independent path to track the interstage gain. Fabricated in a 40nm CMOS process, the prototype ADC achieves a peak SNDR of 66.7 dB and a SFDR of 87.5 dB at 100 MS/s, while consuming 3.7 mW from a 1.1 V supply. The measured Delta SNDR is less than 2.4 dB under +/- 5% supply voltage variation and -20 degrees C-125 degrees C temperature variation.

    2025
    引用
    AI阅读
    加入学术空间
    2A 28nm Floating-Point SRAM-Based CIM Macro with Shifting-in-Memory Exponent Normalization and Mantissa Alignment
    Zhiting Lin, Yang Yang, Miao Long, Hao Li, Rongtao Li, Wenqiang Zhang, Xin Wang,Qiang Zhao,Xiulong Wu, Yu Liu

    In this paper, we introduce a new method for shifting-in-memory exponent normalization and shifting-in-memory mantissa alignment. This approach allows us to add exponents and find the maximum sum simultaneously. We also replace the traditional subtraction and shifting for mantissa alignment with CA and shifting-in-memory operation, enabling FP-CIM to be achieved with lower delay, area, and power overheads. The macro is designed in TSMC 28nm process, with a memory size of 32Kb. Simulation results indicate that the computing core operates at a frequency of 280MHz at a 0.55V supply voltage, and achieves an energy efficiency of 13.5 TFLOPS/W.

    2025
    引用
    AI阅读
    加入学术空间
    3FRIEREN: A Lightweight System for Face Resizing Image Detail Quality Evaluation Via Robust Estimation of Image Naturalness
    Yuan-Kang Lee, Kuan-Lin Chen, Jian-Jiun Ding

    In real-time video conferencing systems, webcams often apply image resizing methods, such as nearest-neighbor, bilinear, bicubic, and Lanczos interpolation, to highlight facial regions and enhance user experience. However, interpolations introduce significant high-frequency artifacts that distort perceived image quality. Our work discovered that existing state-of-theart image quality assessments (IQA) greatly overestimate the sharpness in images resized by nearest-neighbor interpolation, failing to extract useful information in the image's high-frequency components. To address this, we propose FRIEREN (Face Resizing Image Detail Quality Evaluation via Robust Estimation of Image Naturalness), a novel IQA for detail quality evaluation that integrates measures of image naturalness, including motion noise, spatial noise, and HVS-based sharpness. Designed features are fed to Kolmogorov-Arnold Networks (KANs) for quality prediction. Experimental results show that FRIEREN effectively and accurately evaluates the face image detail quality scaled by different interpolations with low computational complexity, making it suitable for quality-aware vision systems.

    2025
    引用
    AI阅读
    加入学术空间
    4A 6T SRAM Analog CIM Macro for 8-Bit MAC with Input/Weight Partitioning for High Signal Margin and Throughput
    Abhishek Goel, Cheena Singhal,Dinesh Kushwaha,Sparsh Mittal,Sudeb Dasgupta

    This work presents an energy-efficient multi-bit (8-b) current-based analog SRAM compute-in-memory (CIM) architecture for MAC operations. Our key idea is to group 8-bit inputs and weights into 2-bit segments for performing MAC operations. This improves signal margin without requiring external circuitry. We leverage a 1C-2C capacitive network for efficient weight encoding and also use an analog shift-and add technique for accumulating partial sums with only 1C and-4C capacitors, thus avoiding the need for higher capacitor values. This approach enhances charge redistribution efficiency and minimizes ADC overhead. The proposed design features a 64x128 6T SRAM array, which can perform 2048 8-bit MAC operations in four cycles with a latency of 15ns. The architecture is implemented in TSMC 65nm technology at 1.2V. The architecture maintains linear MAC operations across different input and weight cases and process corners. The proposed CIM macro delivers a throughput of 136.5 GOPS and MAC energy efficiency of 6.18 TOPS/W while maintaining a signal margin of 32 mV. Our approach achieves an inference accuracy of 98.62%, 90.38% and 69.46% on MNIST, CIFAR-10 and CIFAR-100, respectively.

    2025
    引用
    AI阅读
    加入学术空间
    5A 1D Squeezenet-Based Edge Computing System for Arrhythmia Classification in the Elderly
    Feng Jiang, Yang Wei Lim,Siti Anom Ahmad,Faisul Arif Ahmad, Luthffi Idzhar Ismail,Ahmed Faeq Hussein,Fakhrul Zaman Rokhani

    This paper proposes an edge computing system for real-time arrhythmia classification in the elderly, leveraging a novel one-dimensional SqueezeNet optimized for ECG signal. The special design of Fire Module leverages point-wise (1x1) convolutions to compress channel dimensions and combines them with wider (3x1) convolutions to effectively balance parameter efficiency and temporal feature extraction. By directly receiving the raw input, unnecessary signal conversion operations are effectively avoided. The compact architecture (0.36 million parameters) attains 91.41% accuracy, 99.56% recall, 98.56% precision, and 99.06% F1 score on the MIT-BIH Arrhythmia Database. These results show better performance for classifying previously unseen data of the proposed model than the state-of-the-art works. Evaluated only on elderly subjects, accuracy rises to 96.25% without any decline in other performance metrics, emphasizing the necessity of conducting separate training for the ECG of the elderly. The trained model is quantized and deployed to an Arm Cortex-M7 processor, yielding an inference latency of 146 ms with only 121 kB RAM usage to enable on-device processing. This demonstrates that high-performance elderly-specific arrhythmia classification can be realized on resource-constrained edge computing system without cloud dependency.

    2025
    引用
    AI阅读
    加入学术空间
    立即登录,查看全部 3157 篇论文

    高被引作者

    作者引用发文
    Chao-Tsung Huang4742
    Zhongfeng Wang31224
    Haruo Kobayashi28717
    Nobukazu Takai21711
    Jun Lin2117
    Danyang Zhu2022
    Siyuan Lu1921
    Meiqi Wang1921
    Liang-Gee Chen1784
    Pc Tseng1571

    高产作者

    作者引用发文
    Chua-Chin Wang15126
    Zhongfeng Wang31224
    Rui Paulo Da Silva Martins12023
    Nozomu Togawa14521
    Masao Yanagisawa13920
    Haruo Kobayashi28717
    Chip Hong Chang13916
    Satoshi Goto10216
    Kiat Seng Yeo7115
    Yoko Uwate2514

    相关期刊

    Custom Integrated Circuits Conference
    International Conference on Electronics, Circuits, and Systems
    International Conference on ASIC
    Latin American Symposium on Circuits and Systems
    New Circuits and Systems Conference
    IEEE Nordic Circuits and Systems Conference
    The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS
    Digest of technical papers. IEEE International Solid-State Circuits Conference
    Asian Solid-State Circuits Conference
    IEEE International Conference on Solid-State and Integrated Circuit Technology