Despite increasing efforts to automate analog integrated circuit sizing, manual methodologies remain dominant due to their superior handling of design trade-offs. This work investigates the impact of score shaping functions on convergence speed and Pareto optimality in automated sizing. A case study on sizing a telescopic Operational Transconductance Amplifier (OTA) in the open-source IHP-130nm technology node using Differential Evolution demonstrates that the proposed sigmoid-based score normalization achieves faster convergence and improved design quality compared to traditional linear-based functions. Additionally, we present SpiceXplorer, an open-source, highly customizable circuit optimizer, and discuss its potential integration into future agentic workflows for fully automated design.
This work presents an automated methodology for optimizing fourth-order continuous-time sigma-delta modulators (CT-SDMs) based on the Cascade of Resonators with Feed-Forward (CRFF) architecture. The approach uses the Differential Evolution (DE) metaheuristic to explore the continuous design space and automatically synthesize the loop-filter coefficients, including feed-in, feed-forward, and resonator parameters, without manual tuning. A multi-objective cost function guides the optimization by maximizing the signal-to-noise ratio (SNR) while enforcing constraints related to integrator linearity, stability, and practical implementation. The optimized coefficients are then mapped to physically realizable circuit components for a future implementation in a 22-nm CMOS process with a 2.5 V supply, maintaining consistency between the behavioral model and the circuit-level design. The methodology is validated through simulations using a fourth-order CT-SDM operating at a 32 MHz sampling frequency, with a 125 kHz signal bandwidth and an oversampling ratio of 128. The results demonstrate high performance and illustrate a design flow that is both automated and scalable.
The increasing power demands of data centers necessitate high-efficiency, high power-density DC-DC converters capable of large voltage conversion ratios to step down high bus voltages (48V–60V) to low load voltages. This paper proposes a modified Dual Inductor Hybrid (DIH) Dickson DC-DC converter that achieves a 3-to-1 voltage conversion ratio with enhanced power density and reduced converter volume. The proposed topology integrates a Dickson switched-capacitor network with a dual-inductor buck stage, employing a novel switching scheme that evenly discharges the charge stored on the flying capacitors to the dual inductors. This approach reduces the required inductor current rating, enabling the use of smaller inductors without compromising ripple current headroom, thus minimizing passive component volume. Compared to prior work, the proposed converter achieves a 38.5% reduction in the converter total volume while maintaining equivalent efficiency under a load current of 15 A. Key contributions include a detailed analysis of conduction and switching losses, inductor and capacitor selection criteria, and a comprehensive comparison with a conventional unbalanced DIH converter, demonstrating the proposed design’s volume advantage and the higher inductor current required in a comparable DIH converter.
Accurate performance estimation of radio frequency (RF) integrated circuits (ICs) after placement and routing (P&R) is essential for accelerating design cycles and ensuring post-layout reliability. This paper proposes a vision transformer (ViT)-based framework as a high-speed surrogate model for RF P&R performance prediction, specifically for Low-Noise Amplifier (LNA) layouts. Utilizing an RF specialized dataset comprising 21-channel grayscale representations of routing and via layers based on placement configuration, we treat multi-layer layouts as sequences of patch embeddings to capture global spatial dependency. The ViT model is evaluated on both classification and regression tasks, targeting forward gain $\left(s_{21}\right)$ and noise figure (NF). Experimental results demonstrate that our proposed ViT method achieves competitive accuracy up to $\mathbf{9 7 . 3 \%}$ for classification and an $R^{2}$ of $\mathbf{0 . 9 0}$ for regression. Notably, the ViT architecture exhibits superior computational efficiency, reducing training time by up to 47% compared to the traditional benchmarks like DenseNet-121 and ResNet-50. Our findings suggest that the global attention mechanism of ViT effectively models long-range interconnects, offering a scalable and time-efficient alternative for RF layout performance prediction.
This work presents a silicon-aware evaluation of a low-complexity, and energy efficient single-layer Adiabatic Capacitive Neural Network (ACNN) for Artificial Intelligence (AI) systems. We show that a drastically simplified singlelayer architecture can deliver reliable and efficient computation, highlighting its potential as a scalable building block for energy-constrained AI applications. Implemented in a commercially available $\mathbf{1 8 0} n m$ CMOS technology, the network achieves a classification accuracy over 77% (across corners and temperature) in the arrows8 dataset, within a few percent of a software Artificial Neural Network (ANN) baseline, while maintaining 5x energy savings when benchmarked against conventional CMOS design.
