This study investigates the impact of advanced noise removal techniques on Text-to-Speech (TTS) performance for low-resource languages, focusing on Armenian as a case study. Text-to-speech systems for low-resource languages often perform poorly due to limited and noisy datasets. The hypothesis is that applying state-of-the-art noise removal methods can significantly enhance TTS quality in these challenging scenarios. Using the Armenian subset of the Common Voice dataset, a baseline was first established by training a Tacotron2 TTS model on the original noisy data. SpeechBrain, an advanced speech processing toolkit, was then applied to clean the dataset. A second Tacotron2 model was trained on this noise-reduced dataset. Both models were evaluated using subjective Mean Opinion Score (MOS) tests. The results demonstrated an improvement in TTS quality for the model trained on the noise-removed dataset, with a 10.3% increase in MOS compared to the baseline. This study highlights the potential of noise removal techniques, specifically SpeechBrain, to boost TTS performance in low-resource scenarios, paving the way for improved speech synthesis in a wider range of languages. The findings have important implications for developing more inclusive and higher-quality TTS systems for underrepresented languages.
Advances in field-programmable gate array (FPGA) technology have led to their widespread adoption in various applications, from embedded systems and data centers to high-performance computing. FPGAs provide a flexible and cost-effective solution for implementing digital logic, offering a unique balance between performance, power consumption, and reconfig-urability. The ability to generate and load the FPGA's configuration data, known as the bitstream, is a crucial aspect of FPGA-based system design, as this bitstream defines the FPGA's functionality and behavior. Recently, architectures that integrate FPGA technology with embedded processors have become increasingly popular, enabling the creation of highly versatile systems-on-chip. In this work, we introduce a design methodology that employs open-source tools to enable the generation of FPGA bitstreams directly within embedded processors. This approach harnesses the advantages of FPGA-based systems, such as their reconfigurability and high-performance characteristics, while smoothly integrating them with embedded processors. Additionally, we propose several research directions and applications where this novel paradigm can be leveraged to develop innovative solutions.
The presence of delay faults and addressing them in high-speed digital circuits is an important and challenging task in industries. Delay faults affect the performance of the circuits. To detect such delay defects and assure the timing accuracy of the circuit delay testing plays a critical role. In this paper, a brief of delay testing techniques with emphasis on path delay fault testing is reviewed. A review presented in this paper highlights significant delay test methodologies with the assumption of its greater impact in the future than it has now. We also used the path delay fault testing to detect the infected integrated circuits with improved fault coverage.
Industrial Internet of Things (IIoT) has transformed the traditional industrial processes into smart sensor-centric processes where data can be communicated wirelessly, stored in cloud and evaluated using advanced algorithms. In this approach, it is very important to handle sensor's data while multiple sensors spread within a larger geographical area and making the precise decision. LoRaWAN plays a key role in numerous applications while handling sensor data. This paper explores the potential of LoRaWAN in the Industrial Internet of Things (IIoT). The long-range, and lowpower capabilities of LoRaWAN plays an important role to increase operational efficiency, safety, and sustainability in many industries. The case study shows that LoRaWAN is a strategic enabler to IIoT innovation and sustainability despite of its challenges such as scalability, interference, and security.
Using a machine learning system for testing involves several attempts in an iterative approach. Executing these trials concurrently on an Apache Spark cluster is a popular method. Due to Apache Spark's adherence to the Bulk Synchronous Parallel paradigm, trials are executed in parallel over several phases, separated by obstacles. This implies that all trials from the previous stage have to be completed in order to start a new set of trials. Because of this, we frequently wind up squandering a great deal of time and computational resources on unproductive experiments that should have been terminated quickly. In an effort to tackle these issues, we have developed an open-source system using MAGGY, which uses TensorFlow and Apache Spark to facilitate asynchronous and concurrent hyperparameter tuning and ablation investigations. Better resource use, ablation studies, and hyperparameter tuning are all made possible by this framework under a single expandable API
The method of design of sense amplifier that takes into account reliability issues is presented, where the lifetime of transistors has become longer. Aging simulation results with self-heating (SHE) are improved with the help of circuit architectural changes. At the end-of-life (EOL) the offset degradation has been reduced up to 4%. Also, the heating of the transistors has been decreased due to power reduction. Various industry standards, including Double Data Rate (DDR), Universal Chiplet Interconnect (UCI), Universal Serial Bus (USB), and Peripheral Component Interconnect (PCI), can use the provided structure in specialized input and output circuits.
Limitations of traditional charge pump architectures are investigated, particularly in the context of low voltage operation and reliability challenges. To address these challenges, two all PMOS charge pumps are proposed, one with a four-phase clocking scheme and another with a six-phase clocking scheme. The proposed structures offer enhanced protection against voltage overstress and higher efficiency at low supply voltages. Both traditional and proposed pumps are designed in 14nm process using same sized pumping capacitors, equal clock frequency and output loading to fairly evaluate the efficiency and longevity of the different designs. Results demonstrate that the proposed designs can provide high pumping efficiency at low voltage processes without overstress.
In a rigorous formulation, we consider a boundary value problem of a concentrated electromagnetic field source exciting a conical structure. This structure is a semiinfinite circular semitransparent cone with longitudinal slots cut periodically from the cone tip. By means of the Kontorovich-Lebedev integral transformations, the solution of the original electromagnetic problem is reduced to solving a singular integral equation. An analytical solution for a solid semitransparent cone and a scattered field pattern for a perfectly conducting cone with a longitudinal slot are presented.
With data rates rising and supply voltages falling in applications involving high-speed IOs, the requirement for more stable power integrity at the device, package and board has grown more crucial, as noise criteria have gotten even more stringent. On the other hand, the extensive use of power gating in modern microprocessors to reduce the power consumption of the chip is bringing in problems related to the high current spikes, which have bad effect on power integrity. The method shown in this paper intends to decrease current during switching on due to increasing time of switching, which provides us a lower impact on power integrity, so this will reduce the area of the decoupling capacitors and, because of this, the high-speed IO size can be reduced or, more importantly, this will make it possible to increase the number of work units, improve functionality.
Handwriting recognition is a critical technology for applications like digital document processing and real-time transcription. This paper presents the implementation of a handwriting detection neural network on a Field-Programmable Gate Array (FPGA) to achieve high efficiency and low latency. First the neural network is trained using Keras in Python, and then a quantization algorithm is applied on the parameters of the trained model. The obtained lightweight Neural Network model is used to implement the Verilog model that will be used for the classifier deployment on FPGA. Using quantization and parallel processing strategies, the Network is optimized and then the obtained weights are used in the FPGA-based implementation. Experimental results show that our FPGA-based solution significantly improves processing speed and power consumption efficiency while maintaining competitive recognition accuracy. These achievements indicate the capability of the classifier for real-time handwriting recognition in embedded and edge devices.
The landscape of smart home devices has become very wide in recent years. Many various products are available to consumers ready to be used. The state of security of smart home devices is, however, unknown. The goal is to examine the security state of current smart home devices. The specific categories of smart home appliances are selected. The devices from these categories are then analyzed from different security perspectives. The methodology was based on penetration testing methodology, with adjustments for IoT devices. The results of the analysis are then compared with existing overviews of IoT vulnerabilities.
Fueled by the need to power the artificial intelligence revolution, the semiconductor industry is currently experiencing remarkable growth. This has placed a renewed emphasis on the need to develop new computer-aided-design tools for the efficient and accurate electronic design automation of modern integrated circuits and systems. One emerging component with various applications in neuromorphic computing is the memristor. Due to the promising applications that can be realized with memristors, it is crucial to develop and integrate new models in different simulation environments that allow the characterization and capture of nonlinear memristor behavior. In this paper, the Harmonic Balance formulation of a nonlinear memristor model is presented. We show how a full Harmonic Balance simulation can be performed using this model on sample circuits which opens the door to automated and fast steady-state simulations of arbitrary circuits containing memristors.
A solution for fully integrated on-chip resistance calibration method is proposed. The solution uses stable clock frequency as a reference instead of an on-board high precision resistor. This stable clock frequency is widely available in communication interfaces where impedance matching is crucial. The accuracy of the calibration is limited by the process variance of the integrated MOSFET capacitor which is much tighter than the variance of on-chip poly, metal, or transistor-based resistances. The capacitor is charged to VDD during the clock pulse via a switch and discharged through the digitally controlled resistance during the passive half-period of the clock. The voltage on the capacitor is monitored via a low offset comparator and when it reaches down to the reference level for the first time the digital controller stops the calibration process and stores the code. The proposed solution achieves ±5 accuracy after parasitic extraction and is well within the ±10% specification of high-speed communication interfaces.
The majority of EDA tools exist under Linux. Testing requirements for EDA tools include common factors as well as product specifics. Factors such as software delivery time (SDT) or software quality (SQ) play a significant role for winning the market. However, having a testing framework for EDA tools allowing acceptable SDT and SQ is also a challenging task as there is no ready solution for all products. This work introduces universal methodologies that can be applied by quality assurance (QA) teams to improve STD and SQ of their EDA products.
Assessing the reliability of analog and mixedsignal circuits is a crucial component of the integrated circuit (IC) verification process. This evaluation involves not only examining the circuits’ current performance but also predicting how their functionality might degrade over time due to aging effects. The process of reliability estimation encompasses a range of tests designed to simulate the long-term impacts of aging on the circuit's behavior, ensuring that the IC will continue to operate reliably throughout its expected lifecycle. Existing standard analog and mixed-signal blocks were analyzed by considering one or two methods of increasing circuits’ reliability. Therefore, analog standard blocks have been examined considering aging effects such as voltage threshold, and operating point-dependent degradation, by using MOSRA models. As operating point-dependent degradation has significant impact on analog block's aging, so it should be taken into account while designing aging-aware analog ICs.
This paper presents the development of a framework named DYNAMIC (Dynamic Management Interface for Power Consumption), designed for the dynamic selection of alternative code implementations to minimize energy consumption and extend battery life. The proposed solution works effectively in situations where the device uses energy harvesting. In such cases, the method plans the device power consumption to match the available energy, minimizing the impact on device operation. It is important to note that each device utilizing our framework will be planning its energy budget in-field (and during run time), so each device is optimized within a few days based on its environment of usage. In the experimental section, we present simulation results of experimental power management algorithms for our framework. The results indicate that for our particular study and energy harvester, it was possible to dynamically adjust power consumption so that the user did not notice a significant difference in device performance while achieving a balanced energy budget - under simulated conditions and disregarding battery lifespan, potentially allowing for indefinite operation.
In recent years, number of free cooling system (FCS) applied in datacenters (DC) is increasing due to the provided significant decrease in the electricity consumption and short payback period. However, since FCS is a partially new technology, energy savings potential of FCS has not been sufficiently investigated using real time data series in the literature. In this study, the field measurements and energy performance analysis were performed in an operational DC with water-side free cooling, located in Ankara, Türkiye. Mathematical model of FCS is developed using electricity consumption data of IT devices and FCS, and climate data of Ankara using MS Excel. Electricity consumption of FCS and the PUE of the DC in case of installation of the existing DC in six different climate regions of Turkey were calculated using the developed model. In case of using the FCS, PUE value is obtained less than 1.1 for each location. The result shows that, very low temperatures are not required for the FCS, and the important factor is the number of hours that is lower than the indoor temperature of DC. In case of installation of the DC in Antalya and Şanlıurfa, which are among hottest cities of Türkiye, the electricity consumption of the FCS increased by 8 % and 9 %. However, since the energy consumption of FCS is still much lower than the IT consumption compared to the old type cooling systems, the use of the FCS provided adequate saving.
The authors of the paper investigate the diagnostic features of Hamming codes. The analysis showed that for specific values of the number of bits in the codewords of classical Hamming codes, the check bits are described by self-dual Boolean functions. The authors have established a pattern in which for a certain number of data bits, the check bits of Hamming codes can be calculated by self-dual Boolean functions, and for a certain number by self-quasidual Boolean functions. The encoders of such Hamming codes will be self-dual devices. The encoders of the first codes will be self-dual devices, and the second ones will be self-quasidual devices, respectively. In addition, the same conditions holds true when using its relatively modified Hamming code, for which another check is additionally defined in the form of a parity bit for all data and check bits of the classical Hamming code (extended Hamming code). These features can be effectively used in the synthesis of digital devices and systems with the detection of faults and errors in calculations. This requires the use of a pulse mode of operation and the introduction of temporary redundancy in the operation of the circuits. This makes it possible to use classical and extended Hamming codes in the synthesis of self-checking and fault-tolerant devices with checking of the sign of self-duality and self-quasiduality of calculated functions.
With the development of AI, the models are becoming more complex and resource intensive. There is a need to create smaller but at the same time satisfactory performance models that will run on resource-constrained devices. This paper explores enhancing the efficiency of the MobileNetV2 architecture using the power of the Vision Transformer through knowledge distillation. The goal was to leverage the complex insights of the Vision Transformer to improve the capabilities of MobileNetV2. As a result, the refined model outperformed its original version by about 5% (from 81.7% to 86.5%). The model was then placed on the Coral Dev Board edge device and due to the weight adjustments, there was a slight decrease in accuracy to 84.3%. Despite this, it reduced its processing latency by more than half, from 0.0076 seconds to 0.0037 seconds, proving a valuable approach for efficient and real-time edge computing applications.
Due to the ever-growing use of IP cores in safetycritical applications such as the automotive industry and the varying use cases of every customer, testing these IP cores in alignment with functional safety constraints becomes crucial. Hardware Built-In Self-Test (BIST) methods are commonly employed in such designs, and to efficiently test them, a certain degree of configuration is necessary. We are proposing a method to protect IP cores by not revealing internal hardware to prevent counterfeiting and reverse engineering while enabling flexible examination of diverse test strategies. To prevent inefficient blind configuration of the test hardware, it is crucial to provide information about how configuration impacts test coverage. This work proposes utilizing C++ dynamic libraries to represent an IP core and configure the test hardware model for various testing purposes along with developing gate models that implement an estimation method for test coverage.
