Adapting pre-trained language models to specialized domains is often constrained not only by the quality of the resulting model, but also by the cost of adaptation itself. This is especially important in retrieval systems, where domain shifts can quickly reduce effectiveness and where updates may need to be carried out under limited compute budgets. In this paper, we examine this trade-off for biomedical dense retrieval using a lightweight BERT bi-encoder, comparing full fine-tuning with Low-Rank Adaptation (LoRA). Biomedical search is a challenging setting because user queries are often expressed in non-technical language, whereas relevant documents are written in specialized scientific terminology. We adapt a compact 12.8M-parameter SentenceTransformers model on NFCorpus using a contrastive training objective with in-batch negatives, and we evaluate both retrieval effectiveness (MRR@10, NDCG@10, and MAP@100) and adaptation cost in terms of trainable parameters, training time, and peak GPU memory. Full fine-tuning yields the strongest retrieval performance, while LoRA updates only 24,576 parameters (0.19% of the model) and still retains a substantial portion of the gain at a lower adaptation cost. We also study a larger-batch LoRA configuration, which shortens training time further but leads to a small decrease in retrieval quality. Overall, the results show a clear trade-off between effectiveness and efficiency, and they suggest that parameter-efficient adaptation is a practical option for retrieval systems operating under compute constraints.
Side-channel attacks (SCAs) pose a critical threat to cryptographic hardware by exploiting unintended information leakage such as power consumption and timing variations. In this work, we investigate the susceptibility of AES encryption cores to side-channel vulnerabilities by analyzing how different architectural design choices influence observable leakage. Using a baseline AES RTL implementation as the legacy core, we generated multiple design variants with varying levels of pipelining and parallelization. Each version was evaluated through testbenches in Vivado to measure latency, throughput, and clock cycle behavior. Furthermore, VHDL wrappers were developed to manage complex input/output ports, enabling synthesis and implementation for extracting power consumption metrics, worst negative slack (WNS), and post-synthesis schematics/netlists. Our results demonstrate that pipelining and parallelization significantly impact both timing and power characteristics, thereby creating measurable differences that could be exploited in side-channel analysis. These findings highlight the importance of considering architectural trade-offs not only for performance but also for security, providing hardware designers with insights to improve resilience against SCAs.
This paper presents a power-efficient analog integrated artificial neural network classifier architecture for Electrical Impedance Tomography (EIT)–based stroke classification. The proposed architecture employs a Swish activation circuit, a linearization-expanded Gaussian function circuit, a current-mode correlation stage, and a Winner-Takes-All circuit, enabling progressive nonlinear feature transformation and robust correlation-based inference. The classifier is implemented using energy-efficient analog building blocks and operates from ±0.3V supply rails, achieving ultra-low-power consumption of 590 nW, making it suitable for power-limited biomedical applications. The circuit is designed in TSMC 65 nm CMOS technology using the Cadence IC Suite and verified at both schematic and post-layout levels through corner and Monte Carlo simulations. Validation using a widely adopted EIT stroke classification dataset demonstrates high classification accuracy of 95.95% while significantly reducing energy consumption. These results highlight a balanced trade-off among classification accuracy, power efficiency, and architectural complexity, and demonstrate the potential of analog and mixed-signal neural classifiers as front-end processing solutions for next-generation low-power biomedical machine learning systems.
