The fabrication and characterization of flip-chip assemblies using four polymeric conductive pastes as attachment materials are reported. Three thermoset and one thermoplastic polymeric conductive pastes were investigated. Polymeric conductive pastes having silver particles 2 μm in size made good contact to either smooth or rough metal. Electrical contact with pastes whose particles were 5 μm or larger could only be obtained on rough metal.
Complementary metal-oxide-semiconductor (CMOS) microprocessors operating in the hundreds of megahertz create significant current deltas due to the variation in switching activity front clock cycle to clock cycle. In addition to the high-frequency voltage variations more commonly discussed, a lower frequency noise component is also produced that lasts from 50-200 ns which we refer to as mid-frequency noise. In this paper, we discuss the design of IBM's CMOS S/390 computer for control of mid-frequency noise. This machine has a 10-way multiprocessor on a 127 mm by 127 mm multichip module (MCM) on a FR4 board. The chips on the MCM cause a current step of tens of Amps in a few cycles that can be sustained for many cycles. The power distribution and decoupling capacitors must supply that current without disturbing the voltage level at the circuits. The design of the system power distribution and modeling and verification of mid-frequency noise in this system is presented.
A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 /spl mu/I sample loop; a 0.9-m long, rectangular-shaped (300 /spl mu/m width and 10 /spl mu/m height) capillary column coated with a 0,2-/spl mu/m thick copper phthalocyanine (CuPc) stationary-phase; and a dual-detector scheme based upon a CuPc-coated chemiresistor and a commercially available, 125-/spl mu/m diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual-detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary-phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH/sub 3/) and nitrogen dioxide (NO/sub 2/) when isothermally operated (55-80/spl deg/C). With a helium carrier gas and nitrogen diluent, a 10 /spl mu/I sample volume containing ammonia and nitrogen dioxide injected at 40 psi (2.8 /spl times/105 Pa) ran be separated in less than 30 min.
This paper discusses the frequency and time domain response of embedded passive components in a multilayered structure fabricated using low temperature co-fired ceramic (LTCC) technology. A rational polynomial approximation that combines the accuracy of EM solvers with interpolation methods has been used to capture the frequency dependent losses and parasitics of embedded passives in a macro-model. This method allows for a significant speed-up in computation time while using commercial EM solvers. The macromodel with suitable modification has been used to compute the time domain response in SPICE for typical embedded passive structures. Simulation results show good correlation with time domain reflectometry/time-domain-transmission (TDR/TDT) measurements. The behavior of embedded passives in the high frequency operation of transmission lines and voltage divider networks has also been discussed.
A multigigabit limiting amplifier integrated circuit (IC) for optical transmission system was implemented with AlGaAs HBT technology and packaged in a plastic-molded-bottom-ground air-cavity package using an alpha-staged thermally setting epoxy which comes in a gel in an uncured state. The amplifier was designed to support differential input and output. Small signal performance of the packaged IC achieves 31 dB gain and f/sub 3 dB/ of 4.6 GHz. A single output has 1.0 V/sub p-p/ swing with more than 32 dB dynamic range up to 5 Gb/s. The measured bit error rate applying to APD optical receiver at 2.5 Gb/s bit rate is -33.5 dBm at 1/spl times/10/sup -10/ BER with 2/sup 23/-1 long 2.5 Gb/s NRZ PRBS pattern. The present packaging method was verified by subjecting it to the industry standard condition "c" gross leak test and the overall yield of the air cavity encapsulation process is more than 99%. This method is readily capable of mass production using automated equipment.
A miniature gas chromatography (GC) system has been designed and fabricated using silicon micromachining and integrated circuit (IC) processing techniques. The silicon micromachined gas chromatography system (SMGCS) is composed of a miniature sample injector that incorporates a 10 μl sample loop; a 0.9-m long, rectangular-shaped (300 μm width and 10 μm height) capillary column coated with a 0.2-μm thick copper phthalocyanine (CuPc) stationary-phase; and a dual-detector scheme based upon a CuPc-coated chemiresistor and a commercially available, 125-μm diameter thermal conductivity detector (TCD) bead. Silicon micromachining was employed to fabricate the interface between the sample injector and the GC column, the column itself, and the dual-detector cavity. A novel IC thin-film processing technique was developed to sublime the CuPc stationary-phase coating on the column walls that were micromachined in the host silicon wafer substrate and Pyrex cover plate, which were then electrostatically bonded together. The SMGCS can separate binary gas mixtures composed of parts-per-million (ppm) concentrations of ammonia (NH3) and nitrogen dioxide (NO2) when isothermally operated (55–80 °C). With a helium carrier gas and nitrogen diluent, a 10 μl sample volume containing ammonia and nitrogen dioxide injected at 40 psi (2.8 × 105 Pa) can be separated in less than 30 min.
In order to optimize high-speed systems, designers need tools that automatically generate reduced order SPICE compatible models from geometric descriptions of interconnect and packaging. In this paper, we consider structures small compared to a wavelength, and use a discretized integral formulation combined with an Arnoldi-based model-order reduction strategy to compute efficiently accurate reduced-order models from three-dimensional (3-D) structures. Several issues are addressed including: (1) formulation to insure passivity in the reduced-order models; (2) efficient reduction using preconditioned inner-loop iterative methods; (3) expansion about multiple s-domain points. Results are presented on several industrial examples to demonstrate the capabilities and speed of these new methods
In this paper, a fully three-dimensional model is introduced for the simulation of wire sweep during cavity filling in transfer molding of IC packaging. This includes the composite segment functions for defining spatial wirebond geometry, a singularly numerical integration for calculating flow-induced forces on wirebonds and a three-dimensional penalty finite element technique for simulating molding compound flow. The wire sweep of a 26-leaded device with a die at a given transfer time and molding temperature is studied. The wirebond behavior is investigated in terms of local velocity field and molding compound viscosity etc. The effects of the process conditions, such as transfer time, transfer rate and molding temperature, on wire sweep are also discussed.
The commonly used deposition technology for solder bumps (evaporation or electroplating) requires thin-film processing. The compatibility of the solder-wettable metallizations does not allow the use of the same production equipment as installed in the wafer-fabrication facility. In this study, a maskless bump process is described. Here, solder droplets are ejected from a capillary and impinge on a wettable bond-pad metallizations of electroless-deposited Ni/P-Au. Droplets impinging on rough surface layer often bounce away. It is shown that this roughness layer is mainly determined by the Zn nucleation on the bond-pad metallizations. Nucleation conditions are optimized to deposit only small particles of the same size. The volume of the droplets depends on the product of pulse amplitude and pulse length. Degradation of the interconnection between the piezoelectric actuator and the glass capillary requires a larger pulse amplitude for stable jetting behavior. In addition, it is found that every first droplet on a new position is larger than all other droplets ejected directly thereafter. The diameter distribution of the latter are within the requirements for the final bump. The quality of the solder-jetted bump is studied by several reliability tests after flip-chip assembly on printed wiring boards (PWB's). In combination with underfill, the reliability of solder-jetted bumps are comparable with electroplated bumps.
A novel low temperature deposition process using reactive pulsed de magnetron sputtering has been developed to deposit thin dielectric films composed of either a composite or alternating layers of tantalum oxide and titanium oxide. Capacitors fabricated from these dielectric materials have been found to exhibit exceptional electrical properties. For the composite material, one him containing 22% TiOy had a high dielectric constant of 38, a leakage current density of 10(-6) A/cm(2) at 0.5 MV/cm, and a relatively high breakdown field strength of 2.3 MV/cm. By a slight modification of the deposition conditions, alternating layers of tantalum oxide and titanium oxide were deposited to form a high dielectric constant material, The electrical properties of these films were also exceptional: a dielectric constant of 44, a leakage current density of 3.4 +/- 10(-8) A/cm(2) at 0.5 MV/cm, and a breakdown field strength of 2.3 MV/cm. These films have potential applications in memory and advanced electronics packaging.
IT IS A delight and honor to introduce this special issue of the IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY — PART B: ADVANCED PACKAGING. We feature six works, each of which was presented at ISIS'97, the 1997 IEEE International Conference on Innovative Systems in Silicon. As a showcase for microelectronics systems integration, the conference spans the spectrum from submicron device technology, through design techniques, and computer aided design, to systems architecture. The papers in this issue represent a peer-reviewed consensus of conference highlights, and reflect contemporary trends in applications, miniaturization, testing, and economics. Four of the contributions exemplify how to conceive, design, and implement a silicon system. The other two focus on effective application of technology and engineering resources in evaluating silicon systems.
As supercomputers continue to move toward more powerful processors and parallelization, fast switching structures to route data signals between processors and shared memory become essential, and in fact, may be a primary limiting factor in overall computational throughput. The fast switching network under consideration in this paper is a crossbar switch employing superconducting Josephson Junction (JJ) and multichip module (MCM) technologies. This paper focuses on the design and simulation of the clock distribution network, located within the MCM, that will provide the necessary timing mechanism for data signals traveling through the crossbar switch
In this paper, we present an algorithm for efficient simulation of high-speed interconnects characterized by sampled data. The method constructs pole-zero models of arbitrary interconnects using robust rational approximations of the measured or simulated scattering parameters. In order to obtain accurate interpolations of the data over a wide frequency range, a set of powerful techniques is applied to deal with the resulting ill-conditioned Vandermonde-like approximation matrices. By utilizing the analytic properties of the scattering parameters, the algorithm efficiently generates multiport pole-residue models. The models are combined with the lumped/distributed components for direct time- or frequency-domain simulations. The method can easily be implemented into conventional simulators such as simulation program with integrated circuit emphasis (SPICE) and advanced statistical analysis program (ASTAP) or reduced-order modeling techniques such as asymptotic waveform evaluation (AWE), complex frequency hopping (CFH), and Padd approximation via Lancros Process (PVL) for transient simulation of high-speed interconnect networks. Examples of linear and nonlinear networks are given to demonstrate the validity and accuracy of the method.
This paper discuses the design, materials, fabrication and measurements of a novel integrated decoupling capacitor for MCM-L-based substrates. Based on modeling using the SLA Roadmap, it has been estimated that 13-72 nF/cm/sup 2/ of specific decoupling capacitance will be required for the next decade. The capacitor in this paper addresses this need. The fabrication of the capacitor has been achieved using filled polymer materials in thin film form, with via diameters of 100 um and below, through photodefinable processes. Dielectric constant as high as 65 with loss tangent below 0.05 and specific capacitance of 22 nF/cm/sup 2/ have been achieved. The scattering parameters were measured up to 20 GHz using a network analyzer for various capacitor structures to study input impedance and scaling of the devices. Input impedance of the capacitor is found to be low in the GHz range. The polymer-filled materials and capacitor structures are also scalable to a variety of sizes and values.
We present the design and electrical characterization of a multilayer organic based multichip module (MCM) for use at W-band (75-110 GHz), The ultra-low loss microstrip transmission line on Kapton E(R) (a trademark of DuPont) thin films and benzocyclobutene (BCB) adhesives is reported at W-band. An electrical model for a vertically stacked via interconnect to an integrated circuit (IC) is experimentally developed, This interconnect exhibits very low parasitics and preserves excellent matched conditions for devices and circuits in a module. The electrical performance of the vertically stacked via offers superior performance relative to ribbon and wire bond results reported in the literature at millimeter wave frequencies. We conclude that this technology is capable of realizing compact modules at millimeter wave frequencies.
This paper presents an in depth characterization of thin film microstrip (TFMS) lines fabricated on Dupont PI-2611 polyimide. Measured attenuation and effective dielectric constant is presented for TFMS lines with thicknesses from 2.45-7.4 /spl mu/m and line widths from 5-34.4 /spl mu/m over the frequency range of 1-110 GHz. The attenuation is separated into conductor and dielectric losses to determine the loss tangent of Dupont PI-2611 polyimide over the microwave frequency range. In addition, the measured characteristics are compared to closed form equations for /spl alpha/ and /spl epsiv//sub eff/ from the literature. Based on the comparisons, recommendations for the best closed form design equations for TFMS are made.
This paper reviews the state-of-the-art in three-dimensional (3-D) packaging technology for very large scale integration (VLSI). A number of bare dice and multichip module (MCM) stacking technologies are emerging to meet the ever increasing demands for low power consumption, low weight and compact portable systems. Vertical interconnect techniques are reviewed in detail. Technical issues such as silicon efficiency, complexity, thermal management, interconnection density, speed, power etc. are critical in the choice of 3-D stacking technology, depending on the target application, and are briefly discussed.
The effects of floating conductors in three-dimensional (3-D) packaging structures are investigated. The simulations are based on a frequency-dependent integral equation formulation for the calculation of the magnetoquasistatic current distribution in complex: interconnect structures. The calculated current distributions are used to develop an inductance/resistance equivalent circuit representation of the package that can be used as a subcircuit in SPICE for simultaneous switching noise calculations. The model is frequency dependent and captures the Effect that multiple solid/meshed ground/power planes, pins, vias and traces have on overall package inductive performance, The impact of floating planes, such as a heat spreader under a ball grid array (BGA) structure, on the mutual inductances of the structure is demonstrated. The frequency dependence of the floating plane effects is examined also. The behavior of the induced eddy currents in the floating plane is investigated also, particularly in the vicinity of interconnect discontinuities. Switching noise results obtained using SPICE simulation and the generated inductance/resistance equivalent package models show the effects of floating planes on switching noise.
Mid-range computer performance is fast approaching speeds once considered appropriate for only high-end systems. IBM mid-range computer performance enhancement is enabled by the PowerPC RISC technology and the ability to effectively package the chips to maximize their electrical performance. MCM-D/C, coupled with IBM's controlled collapsed chip connection (C4) offers an optimized solution for high performance modules. This paper describes a state-of-the-art seven chip MCM-D/C package currently under production for use as a processor module for the high end of IBM's AS/400 Advanced Series with PowerPC. The package consist of a 63.0 mm metallized ceramic PGA substrate with 5 levels of Cu-Polyimide nonplanar thin films. It provides the interconnection for 7 high-performance Bi-CMOS logic and memory chips. Each chip has over 2600 C4 connections divided between power, signal and ground. The terminal metal layer provides the C4 pads for chip connection, as well as special repair wiring available for the repair of defects created during the fabrication process. Up to 220 watts are dissipated with air cooling while maintaining high module reliability
