In this paper an integrated J-band (220-325GHz) receiver is presented. It is implemented in a 130nmSiGe BiCMOS technology (ft/f max = 250/370GHz). The receiver consists of a subharmonic mixer (SHM) with additional LO and IF buffers and Marchand baluns for single-ended measurements. The SHM consists of two stacked switching quads with a subsequent cascode IF butter. The stacked switching quads are driven by an in-phase LO signal and do not require a space-consuming 90° coupler. The LO input is fed by the half RF frequency. Measurements within the RF input range of 300-325 GHz show a high peak conversion gain (CG) of 14. 80dB at 320 GHz and a DSB noise Figure of 20dB. The total DC power consumption is 175mW and the dimensions are (200 x 170)$\mu m^{2}$. To the best of the authors’ knowledge, this circuit has the highest broadband conversion gain reported in this frequency range and this SiGe technology.
The theory, design and implementation of a millimeter-wave (mm-wave) common-collector voltage-controlled differential Colpitts oscillator (VCO) using 130nmSiGe:C BiCMOS technology is presented. The VCO was optimized to provide a wide analog-only (continuous) tuning range of 81 to 91 GHz (11.6%) for high-precision radar applications. The analog-only tuning capability makes use of a single varactor pair which eliminates the need for digital control signals, switched-capacitor banks and peripheral digital control/interface circuitry. Thus, this approach simplifies the design of frequency synthesizers for mmwave applications and increases the robustness of operation. The VCO operates with a 3 V supply voltage and achieves a low power consumption of 60mW including the cascode output buffers. It provides a single-ended output power of 4.3 dBm and a phase noise of-112dBc/Hz at 10MHz offset with a 90.5 GHz oscillation frequency. It has a state-of-the-art figure-of-merit-tuning (FoM T ) of -179dBc/Hz.
This paper presents a 295-337GHz high output power, cascode-based frequency doubler, achieving 2.5 dBm saturated power ($\mathrm{P}_{\mathrm{s}\mathrm{a}\mathrm{t}}$) at 312 GHz and 42 GHz $\mathrm{P}_{\mathrm{s}\mathrm{a}\mathrm{t}}$3 dB-bandwidth. Inductive gain enhancement is applied to overcome high interconnect losses and the reduced gain performance above the transit frequency of the available technology. This is achieved by embedding an inductance between the base terminals of the cascode transistors, that provides a strong positive feedback. A peak conversion gain of 15dB is achieved at 312 GHz and remains above 7.5dB for operation at maximum output power. The chip is fabricated using a $130\mathrm{n}\mathrm{m}\mathrm{S}\mathrm{i}\mathrm{G}\mathrm{e}$ BiCMOS technology with $f_{\mathrm{t}}/f_{\max}$ of 250 $\mathrm{G}\mathrm{H}\mathrm{z}/370$ GHz and consumes 535mW from a 3.3V and 3.65V supply, which corresponds to a state-of-the-art drain efficiency of 0.3 %. To the best of the authors knowledge, the power of 2.5 $\mathrm{d}\mathrm{B}\mathrm{m}$ is the highest reported among cascode-based frequency doublers in SiGe HBT technology so far.
This paper presents a CMOS-MEMS tunable phase shifter. Instead of using two identical loadings which are commonly seen in reflection-type phase shifters, this topology only requires a single load, leading to smaller chip size and lower fabrication cost. In addition, the actuator-driven interdigital capacitance is designed to generate nine tuning states, providing more flexible phase tuning. The measurement results show that phase tuning range of ~80° is achieved over the entire band with excellent linearity.
We demonstrate compact spiral-transmission-line (TL)-based Ka-band SPDT (single-pole double-throw) switch and Wilkinson power divider (with CRC isolation network) for millimetre-wave (mm-wave) 5G communications. For the power divider, a parallel capacitor is included at the input port to compensate the imaginary part of the input admittance for input matching. Dual spiral structure with TL length of about $\lambda / 14$ and symmetrical layout is used to achieve compact chip area and small amplitude imbalance (AI) and phase difference (PD). At 28 GHz, the power divider achieves prominent S 11 of -12.1 dB, S 22 and S 33 of -27 dB, S 32 of -17.4 dB, S 21 of -3.989 dB, S 31 of -3.964 dB, AI of -0.025 dB, and PD of 0.171°. The normalized chip area is $9.8 \times 10^{-5} \lambda_{0}^{2}$, one of the smallest normalized chip areas ever reported for mm-wave power dividers. For the SPDT switch, parallel capacitors are included at ports 1-3 to reduce the required TL length of the equivalent $\lambda / 4$ TLs for compact size. For 25-30 GHz, the SPDT switch achieves decent in less than 1.6 dB and isolation better than -30.4 dB.
Accurate on-wafer characterization of differential devices poses a challenge, as it involves multi-mode de-embedding of four-port error networks. In our previous work we have shown that under the assumption of negligible mode conversion, one can separate the differential and common-modes. Thus, one can extract from the $4\times 4$ modal S-parameter matrix two $2\times 2$ quadrants, corresponding to differential and common mode characteristics. One can treat these quadrants as equivalent two-port networks and apply the classical two-port de-embedding techniques. This assumption was verified for symmetrical devices. However, the practical applicability limits of this approach have not been explored yet. Therefore, in this work we investigate empirically the mode-separation method for asymmetrical networks. This can be required for characterization of asymmetrical devices, such as transmission-line-based asymmetrical couplers with a high coupling ratio or transformers. As an example, we characterize an on-chip transformer as device-under-test (DUT) realized in 28 nm bulk CMOS technology. Several asymmetric and symmetric de-embedding structures were fabricated in the same process. A comparative study is performed by applying mode separation approach combined with the Thru-Line (TL) and Thru-Open (TO) techniques to symmetric and asymmetric de-embedding standards.
Limited TX-RX isolation in mm-wave FMCW radar results in self-interference (SI) from TX at RX, impacting RX linearity and noise figure. This work presents a self-interference cancellation (SIC) approach that addresses challenges related to wideband SIC, using a dynamic phase shifter (PS) and attenuator in the SIC path that is capable of emulating delay in the leakage path through canceller-path modulation. The proposed mm-wave LNA with SIC for FMCW radar is implemented in 65-nm CMOS technology with the frontend achieving >30dB SIC across 425 MHz with -8dBm SI. The front-end consumes 33.6 mW from 1. 2V and occupies $1.15\text{mm}^{2}$ of die area.
We demonstrate noninverting single-spiral Ka-band (26.5-40 GHz) CMOS power divider and its quadrature coupler (QC) and balun. For the power divider, a parallel capacitor is included at the input port for matching, and a parallel RC network is connected between the output ports for matching and isolation. Transmission-line (TL) length of about $\lambda/12$ is adopted to achieve miniature area and small amplitude imbalance (AI) and phase difference (PD). Negative and positive phase-shift TLs with phase-shift of -45° (or -90°) and 45° (or 90°), respectively, are included at ports 2 and 3 of the power divider to form QC (or balun). Decent result is obtained. For example, the QC achieves S 11 of -13.5dB, S 22 of -14.5 dB, S 33 of -19.4 dB, S 32 of -10.5 dB, S 21 of -4.713dB, and S 31 of -4.731dB at 28 GHz. AI and PD deviation (PDD) are 0.018 dB and -0.1°, respectively. Moreover, S 11 is smaller than -10dB for 10.4-50 GHz, equivalent to a fractional bandwidth (FBW) larger than 141.4%. The QC occupies a normalized area of $6.1\times 10^{-4}\lambda_{0}^{2}$, one of the smallest normalized areas ever reported for millimeterwave (mm-wave) QC or balun.
This paper demonstrates a 160GHz transceiver (TRX) chip in 130nm BiCMOS technology with localized backside etching (LBE) on-chip antenna array. The Transmitter (TX) is equipped with a vector modulator while the receiver (RX) makes use an in-phase-quadrature (IQ) topology to enable not only multimode radar techniques but also a joint radar-communication (JRC) operation. The chip area is utilized efficiently to synthesize a single $2\times 1$ patch antenna array in a monostatic architecture employing a rat-race coupler which provides 30dB TX-RX isolation in the radar operation mode. Thanks to the silicon LBE capability, the array-on-chip achieves 8.5 dBi. The JRC chip is fabricated and a prototype hardware is manufactured where the effective isotropic radiated power is measured at D-band (110-170GHz) for validation.
A fifth-generation (5G) radio frequency power amplifier (PA) implemented in 45nm COMS SOI technology is presented. The design is based on a stack of six transistors divided into two cells, each with a common source and two common gate stages. The layouts of the three transistors in each cell are combined to reduce parasitic capacitances and improve the PA performance. Under 4.8 V power supply (0.8 V per transistor) and at the operating frequency of 23 GHz, the CMOS PA achieves a saturated output power (PSAT) of 18.2 dBm, a -1dB output compression power (P1dB) of 16.74 dBm and a power gain of 13.1 dB with a peak power-added efficiency (PAE) and drain efficiency (DE) of 33.9% and 40.1%, respectively. Under a larger bias voltage of 6 V (1 V per transistor), PSAT increases to 19.41 dBm while peak PAE and DE slightly reduce to 23.5% and 26.8%, respectively.
This paper presents a two-stage D-band power amplifier (PA) realized in 0.13 $\mu\text{m}$ silicon-germanium (SiGe) BiCMOS technology. The amplifier employs the cascode topology at both stages and achieves a saturated output power(P sat ) of 15 dBm while output referred 1-dB compression point (OPldB) is 11 dBm. The maximum power-added-efficiency (PAE max .) is 7.8% and the small signal gain peaks at 18.2 dB. The presented amplifier occupies an area of $0.83\times 0.52mm^{2}$ including the pads.
This paper presents an innovative x3 sub-sampling frequency downconverter for converting signals around 77 GHz from a 26 GHz LO signal. With a LO frequency divided by 3 this topology allows drastic simplifications on the receiver's LO distribution chain. The sub-sampling mixer operation principle is described and implemented with 2S-nm FD-SOI CMOS technology. Simulation results show a 1dB input-referred compression power (ICPldB) of +3dBm and a 14.4 dB Noise Figure (NF) with a -2.5dB conversion gain. The mixer's LO signal shaper consumption is 36 mW on a 1. 2V supply while the passive mixer core doesn't require DC power.
We present an ultra wideband push-push based frequency doubler with differential outputs and a 3 dB-bandwidth from 4.8 to 80 GHz. The maximum conversion gain is 1.7 dB at 25 GHz and -13dBm input signal. An on-chip active balun provides the differential drive signal enabling a good fundamental rejection over a wide bandwidth. Measurements up to 100 GHz verify the circuits functionality. The output bandwidth of 75 GHz combined with less than 3 dB output power variation exceeds the results of previous publications with differential outputs.
In this work, an ultra-wideband inductorless amplifier implemented in a 45nm CMOS SOI technology is presented. The amplifier operates over a DC to 32 GHz frequency range. The architecture allows a rail-to-rail operation for a supply voltage of 1V. The amplifier achieves 19 dB gain with the input return loss better than -10dB from DC to 12 GHz and output return loss better than -12dB overall bandwidth. The power consumption is 7.8 mW. The core size is only 0.000149 mm2. To the author’s best knowledge, this amplifier provides the highest flat gain over the 32 GHz operation bandwidth and the smallest area compared to similar works in the literature.
This work presents the performance comparison of a V-band T/R amplifier module in a SiGe: C 130nm BiCMOS technology, featuring ft/fmax of 250/340 GHz, realized using two different back-end of lines, Aluminium and copper based. The T/R amplifier-module can be used for integrated/hybrid phased array systems and consists of two SPDT switches, PA in Tx path and LNA in Rx path. Measurement results show that the amplifier-module realized using the copper back-end has about 1 dB higher gain, 0.5 dB higher output 1dB compression point in Tx mode and 0.4 dB lower noise Figure in Rx mode than the one based on the Aluminium back-end. The T/R amplifier-module occupies 1.1mm2 area and consumes 160 mW/50 mW in Tx/Rx modes.
We demonstrate a 77/154 GHz push-push voltage controlled oscillator (VCO) with tail double-frequency ($f_{02}=2 f_{01}$) output in 90 nm CMOS. Off-state parallel transistors (OSTs) are included in the cross-coupled transistors (CCTs) of the VCO to enhance the nonlinearity-based second-harmonic frequency tone. This leads to enhancement of phase noise (PN) and output power $\left(P_{out}\right)$ of the VCO. The VCO consumes 14.4 mW and achieves decent results. For example, at the fundamental (f01) port, the VCO achieves single-ended Pout of -6.8 dBm, tuning range of 7677.6 GHz, and a PN of -109.2 dBc / Hz at 10 MHz offset from the carrier. The corresponding FOM is -175.41 dBc / Hz. Moreover, a 70 / 140 GHz push-push VCO with head f02 output is also implemented for comparison. The VCO consumes 11.8 mW and achieves single-ended Pout of -3.6 dBm, tuning range of 66.3-70.2 GHz, and a PN of -113.8 dBc / Hz at 10 MHz offset at the fundamental port. The corresponding FOM is -180.01 dBc/Hz. To the authors’ knowledge, the PN and FOM of the VCO are one of the best results ever reported for a V-band CMOS VCO.
This paper presents an active BALUN operating around 257GHz with a 40GHz bandwidth. It employs a pseudo-differential cascode stage with a transformer-coupled output and cross-coupled capacitive elimination. Employing multiple enhancements, the common-mode suppression and single-ended to differential conversion are increased. Unaccounted changes during manufacturing are analyzed and included in the simulations. The circuit is manufactured in 130nmSiGe BiCMOS. To the best of the author’s knowledge, it is the first reported active BALUN operating above 200 GHz.
This paper presents an integrated differential, distributed Mach-Zehnder modulator (MZM) driver with two-tap feedforward equalization (FFE). The driver consists of two-stack, pseudo-differential FET stages capable of voltage swings exceeding the VDD (1V). The measured chip produces error-free (BER $\lt 10^{-11})$ NRZ transmission up to 64 Gbps with 0.3 UI sampling margin and four-level pulse amplitude modulation (PAM-4) transmission up to 80 Gbps (40 Gbaud). The total power consumption of the driver is 310 mW for an energy efficiency of 4.8 pJ/bit for NRZ and 3.9 pJ/bit for PAM-4.
This work studies the impact of increase in temperature on the RF and analog figures of merit (FoMs) of 22 nm FD-SOI MOSFETs from room temperature of $25^{\circ}C$ to $175^{\circ}C$. DC and RF measurements are performed on the MOSFETs to extract the main RF FoMs over temperature. From DC measurements in temperature, the zero-temperature coefficient (ZTC) point and threshold voltage (V Th ) reduction on increasing temperature is observed. Through direct on-wafer RF measurements reductions of 21% in the current-gain cut-off frequency (f T ) and of of 14% in the maximum oscillation frequency $(f_{\max})$ are observed at 175°C compared to $25^{\circ}C$. In particular, the evolution over temperature of trans conductance $(g_{m})$ appears to be one of the major causes of the degradation in f T and f max .
A multiplying outphasing transmitter (MOT) based on a reflection-type phase shifter (RTPS) and multiplier chain is demonstrated at 120 GHz. The input signal is split into two paths with a lumped element Wilkinson power divider and two differential RTPS phase shift the signal for outphasing modulation. The prototype MOT is fabricated in Global Foundries 22nm FDSOI CMOS process and the measured transmitter performance achieves 1.4% DC-to-RF efficiency with 5.9 dBm output power at 116.4GHz.
