Over the years, the technology of designing and manufacturing electronic devices has evolved dynamically, introducing new possibilities in the production of integrated circuits and systems. Despite advancements, significant challenges remain. This paper aims to highlight interesting research directions related to hardware design that are crucial from an industrial perspective. The presented problems will be supported by examples from real-world projects, including Open Hardware, Chiplets, and security issues such as supply chain attacks, side-channel vulnerabilities, and quantum computing threats.
The use of Machine Learning (ML) mechanisms for image analysis in dentistry may potentially bring many benefits. At the same time, potential challenges may include the availability of dental images, the availability of specialist imaging equipment, and the selection of an appropriate ML model. The main goal of this paper is to propose a procedure for designing an ML-based module of a dental system for analyzing dental images, using the example of a tooth detection algorithm within images obtained from popular devices such as a camera or a smartphone. As part of this paper, a review of open access dental image datasets with assumed characteristics was conducted, followed by a review of ML models used for tooth detection. Next, a proposal for the architecture of a tooth detection module was developed along with a prototype implementation version. The works carried out also constituted an extension of the DentIO system, enabling, among other things, the generation of dental diagrams based on voice commands. Further research directions may include expert verification of the results presented based on dental knowledge, as well as extension of the format of the analyzed data to include dental video analysis.
This article presents a step-by-step process for modeling and analyzing the Space-Time Averaging Phase-Locked Loop architecture, which enables fractional frequency synthesis while significantly reducing the quantization error caused by fractional division. This reduction is achieved through the use of spatial averaging implemented as array of dividers, phase-frequency detectors, and charge pumps. A tree-structured, switching-block -based digital encoder is employed to generate the control signals for the dividers. The critical part of the design from the loop dynamics point of view is implemented at the transistor level using TSMC 40nm CMOS technology, while the reminder is modeled in the Verilog-A Hardware Description Language. The analysis focuses primarily on the fractional spurious tones originating from the quantization error. The Discrete Fourier Transform is used to obtain the output frequency spectra of the space-time and time averaging to evaluate the effectiveness of spatial averaging in reducing quantization noise.
In this work we present an application of Particle Swarm Optimization (P50) algorithm as a support in the design of Finite Impulse Response (FIR) filters. The conventional PSO algorithm was not sufficient to obtain desired filter parameters for filters longer than 20 coefficients. For this reason, we used an adaptive PSO algorithm that allows for adjustment of several key parameters during the optimization process of the swarm. In comparison to existing adaptive algorithms, in which for example only the inertia coefficient was subject to change, in our approach the possibility of changing several parameters simultaneously has been introduced. In our approach we additionally modify the social and cognitive coefficients in parallel. As a result, it was possible to obtain satisfactory results for FIR filters of lengths exceeding 50. In this work, we focused in particular on examining the effect of the swarm population size on the algorithm convergence. It turned out that for FIR filters of lengths around 40-50, satisfactory results are obtained with the number of particles in the swarm at the level of 100-150.
In this work we discuss and evaluate different approaches to solving anomaly detection task when the target platform is a tiny microcontroller. We investigate modeling techniques and propose a comprehensive set of measurements to analyze performance, compute and memory requirements, and power efficiency. We run experiments to collect these measurements on platforms used in TinyML systems including Cortex-M7, Cortex-M55 and Ethos-1.155 running TensorFlow Lite for Microcontrollers. The measurements arc collected for an autoencoder in reconstruction -based anomaly detection and a MobileNetV2-like model trained for classification. We show which approach is more suitable depending on the system requirements and constraints. This work underscores the need for a holistic approach in selecting modeling and deployment strategies, providing empirical evidence to guide the development of efficient on-device anomaly detection systems.
The main contribution of this paper is a new approach to semi-automated synthesis of Application Specific Embedded Processors (ASEPs). Designers of ASEPs do not have the comfort of standardized software support because the instruction sets are customised. Therefore, ASEP designs are frequently performed manually. However, in recent years a growing interest in ASEPs has been observed. This can he explained by the following two factors. Firstly, in contrast to general-purpose processors, ASEPs are particularly resilient to cybersecurity threats, which nowadays affect both software and hardware in modern SoC applications, especially in critical areas such as medicine, communication or smart grids. Secondly, the usual justification for using ASEP designs is their excellent performance and power efficiency characteristics which are comparable or can exceed those of dedicated hardware. Results presented in this paper show that automated ASEP designs can be more than an order of magnitude smaller, and therefore more power efficient, than equivalent general-purpose application specific embedded processors. The small size results from the fact that both the architecture and instruction set of an ASEP are tailored to the unique needs of a particular application within the embedded system. The automation approach presented in this paper helps to reduce the high design costs and necessity to use highly skilled design engineers.
Efficient RF amplification and power combination are key challenges in 5G/6G transceivers. In particular, Power Amplifier (PA) designs have to balance linearity and efficiency requirements to accommodate high Peak-to-Average Power Ratio (PAPR) waveforms, and power combining networks such as Wilkinson combiners introduce insertion losses, limiting the achievable energy efficiency of the RF Front-End (REEF:). This work explores Power Combination Over-the-Air (PCOA), where four sinusoidal components are individually amplified by an RF PA operating at near saturation, driving a 4x4 patch antenna array. Though beamforming, the components are spatially power combined, in the far-field. PCOA allows more efficient PAs to be used, reduces interference to other systems, and avoids circuit -based power combiner disadvantages. A high-level system model is developed to analyze the influence of per-component power control, PA sizing, and antenna array configuration on PCOA efficiency and directivity. Nonidealifies such as noise, PA distortion, impedance mismatches, path loss, and mutual coupling are considered, providing insights into optimal PA output power levels, beamforming strategies, and array design trade-offs. Simulation results show that PCOA can decrease RFFE losses, making it a promising technique for next-generation transceivers.
The deployment of machine learning (ML) systems at scale necessitates a robust, flexible, and well-orchestrated infrastructure. Azure Kubernetes Service (AKS) has emerged as a key platform for managing ML workloads, offering scalability, automation, and integration with cloud-native AI services. This article explores the fundamental design principles for architecting ML systems on AKS, focusing on scalability, security, cost efficiency, and operational reliability. Key architectural considerations are analyzed, including cluster resource management, model training and deployment strategies, and observability practices. Furthermore, security and governance frameworks are examined to ensure compliance and data protection in ML workflows. Real-world case studies and best practices illustrate successful implementations of ML on AKS across various industries. Finally, emerging trends and challenges are discussed, emphasizing the continuous evolution of Kubernetes-based ML infrastructures and the need for adaptive design strategies in cloud-native AI ecosystems.
High-level synthesis tools help engineers deal with the challenges of building complex systems that use reconfigurable technologies. Such serves as a precursor to well-established methods in the software industry, such as Test-Driven Development, in the development process of hardware components of an embedded system. However, the assistance offered by the high-level synthesis validation tools could he strengthened and targeted at the early stages of project development. This paper describes a hardware testing framework as a means to quickly evaluate the capabilities of embedded components using a unit testing paradigm, leading to Test-Driven Development implementation on recontigurable hardware.
We investigate the behaviour of a bio-inspired artificial neuron, implementing a simplified Morris-Lecar model under downscaled supply voltages in the subthreshold regime towards ultra-low-power performance. The neuron spike characteristics, including amplitude, period, and typical shape, are analysed as the supply voltage is reduced. We observe a dramatic loss of the typical linear-exponential behaviour in the rising edge of the spike related to a drastic reduction in spike amplitude and an increase in spike period. These are used to define figures-of-merit of spiking operation for ad hoc neuromorphic computations. Subsequently, through Monte Carlo variability analyses, we highlight that ultra-low-voltage neurons are highly sensitive to process variations and prone to statistically likely failures. Our study evidences the challenges of maintaining stability and performance in low-power neuromorphic circuits and the importance of reliability assessments.
The article presents an analysis of selected cryptographic algorithms for their application in data transmission in airborne networks, as well as other devices that use microcontrollers, such as Internet of Things (IoT) devices. Different types of microcontrollers used in Unmanned Aerial Vehicle (UAV) platforms are presented. The ESP32 microcontroller is used for hardware testing. A selected set of lightweight cryptography algorithms is implemented in the microcontroller to test their computational efficiency. The tests for AEAD algorithms include: ChaChaPoly, ASCON-128, TinyJAMBU, ISAP, and PHOTON-Beetle, and for Hashing algorithms: BLAKE2s, ASCON-HASH, and PHOTON-Beetle-HASH.
This paper analyzes the thermal behavior of lateral (Vertical Slit Transistor Integrated Circuits, VESTIC) and vertical BJTs on SOI substrates, focusing on self-heating effects, heat dissipation mechanisms, and thermal stability. The buried oxide (BOX) layer in SOI significantly impacts heat Bow, leading to localized hot spots in vertical BJTs and more distributed heating in lateral BJ'Is. Using numerical simulations and experimental data, we evaluate thermal management strategies and their implications for complementary bipolar logic (CBip). 'I'he findings highlight the need for optimized device layouts and biasing techniques to mitigate self-heating, ensuring stable and efficient operation of SOI-based bipolar circuits.
FPGA devices are complex entities which can draw extremely high currents from low voltage rails. This presents multiple problems during the design of power supplies for FPGA circuits. In this paper, an electronic load capable of replicating the current draw from FPGA circuits will be introduced, which will streamline the design of low-voltage, high-power supplies and enable robust testing of designed electrical power rails. Designing electronic loads is a complex procedure, it requires careful design of the schematic, special considerations for the layout to keep the resistance within budget, and additional thermal considerations must also be taken into account.
This paper examines interesting natural language modelling tasks, such as word-based and subword-based language modelling, where deep learning methods are making some progress. Language modelling helps to predict the sequence of recognised words or subwords and thus can be used to improve the speech recognition process. However, the field of language modelling is currently witnessing a shift from statistical methods to recurrent neural networks and deep learning techniques. This article focusses on an example of using recurrent LSTM neural networks for language modelling and speech recognition. The new research results presented in this paper, following on from previous papers, focus on how to develop word-based and subword-based LSTM language models and how to use them together. The simultaneous use of both LSTM language modelling methods allows for the development of hybrid language models that have even better properties and can further improve the speech recognition process. The results presented in this paper apply to Polish language modelling, but the results obtained and the conclusions formulated on their basis can also be applied to language modelling applications for other languages.
The paper presents the results of measurements of the characteristics of selected power LEDs mounted in COB packages. The operation of this class of semiconductor devices without any additional cooling system, with a classic aluminium heat-sink and with a liquid cooling system with a heat exchanger were considered. The structures of the tested diodes and the measured current-voltage characteristics of the tested devices operating in the forward and reverse modes, the dependence of the luminous flux and thermal resistance on the forward current and the waveforms of the illuminance of the emitted light were presented. The obtained measurements results were discussed. Particularly, an influence of self-heating phenomena on the obtained characteristics was considered.
This article discusses the Operational Transconductance Amplifier (OTA), which is a part of the integrator circuit for the new read-out electronics for the FIT detector in the ALICE experiment in CERN. The circuit is implemented using 180nin CMOS technology within Cadence Virtuoso, and powered by a 3.3 V supply. This design features a two-stage, single ended CMOS operational transconductance amplifier (OTA) incorporating cascodes, along with a load capacitance of 50 pF. This solution allows for the processing of nanosecond pulses across a broad dynamic range.
This paper presents a novel approach using levelcrossing ADCs (LC-ADCs), which provide a more powerefficient solution by sampling only when the input signal exceeds predefined amplitude thresholds. A 6-bit LC -ADC architecture that eliminates the need for an n-bit DAC and uses a single comparator, incorporating integrated sample -and hold and logic functions, is proposed. This design drastically reduces power consumption while maintaining accuracy, making it particularly suitable for low -power biomedical applications. Simulation results in 180 nm CMOS technology with 1.8-V power supply demonstrate the system's high performance, including a Figure-of-Merit (FoM) that outperforms traditional designs. The proposed LC-ADC architecture is shown to he highly efficient, with significant reductions in power usage and FoM to 9011111 and 0.115 fJ/step, offering an ideal solution for long-term, energyconstrained biomedical signal monitoring.
Industrial communication in hazardous areas requires protocols that guarantee safety, reliability and efficiency. The aim of this study is therefore to compare the characteristics of Process Fieldbus for Process Automation (PROFIBUS PA), Fieldbus Foundation and Ethernet Advanced Physical Layer (Ethernet-APL) applied in hazardous areas, considering not only their technical differences, but also their ability to provide intrinsically safe communication inside of an industrial environment.
The choice of Verilog-A as an approved semiconductor device hardware description language for IC design has encouraged the interchange of standardised Verilog-A BJT, MOST and BICMOS device models across commercial and FOSS circuit simulators. Recent trends have seen the release of openaccess IC production development kits for digital, analogue, RF and mixed analogue/digital design, completing the "circuit concept to IC production" cycle with FOSS software tools. This paper is concerned with an extension of modelling, simulation and parameter extraction of analogue IC cells using Ques-S/Ngspice and the HIP-G130G2 PDK. To illustrate these techniques an investigation of a CMOS analogue single ended active inductance cell is presented together with simulation output data and extracted model parameters for 1.30nm thin and thick oxide CMOS devices.
This paper presents an optimized approach to designing OTA-C filters with a focus on reducing the number of components while maintaining or improving performance. By employing shared sub-blocks within the transconductance amplifier architecture, the proposed method minimizes power consumption and circuit area, ensuring efficient integration in modern electronic systems. The paper also discusses the theoretical basis for the design, implementation details, and performance evaluation of the optimized filters. The results demonstrate significant improvements in resource efficiency and scalability compared to conventional designs.
