Sub-sampling PLLs use a transconductor following the sampling phase detector. To reduce the loop-filter capacitor size, a small transconductance with polarity switching can drive a switched-capacitor loop filter; however, slow settling introduces uncertainty in the PLL parameters, and excess output noise directly contributes to PLL jitter. Realizing a small transconductance at low bias current results in slow switching, whereas large bias currents with current cancellation degrade noise performance. Additionally, the transconductor must maintain high output impedance and a sufficiently large control-voltage swing. The proposed feedforward gain-boosted cascode transconductor achieves 80 dB dc gain and less than 2 ns settling time, enabling a prototype 24.6–29 GHz SSPLL with a 50 MHz reference to achieve −97 to −100 dBc/Hz phase noise at 500 kHz, −118 to −120 dBc/Hz at 10 MHz, 236–246 fs rms jitter, 22.3–25.3 mW power consumption, a 266.4 dB FoMj,N, and a 0.136 mm2 area in 65 nm CMOS. The PLL loop parameters are accurately controlled, and the transconductor contributes only a small fraction of the total jitter. The proposed feedback loop architecture is applicable to other high-gain opamp systems operating with low bias currents.
Content-addressable memory (CAM) is essential for data-intensive applications such as network packet classification, but conventional row-by-row architectures store one fixed-width rule per row, so variable-length rules must be padded to the row width, limiting the average array utilization to 53.1% for a representative uniform 1–16-byte rule-length distribution. This letter proposes a reconfigurable CAM architecture that raises array utilization to near 100%. A reconfigurable segmented array (RSA) with match-line switching circuitry (MSC) stores variable-length rules consecutively at arbitrary starting positions without inter-rule padding, and an input cyclic self-alignment (ICS) mechanism keeps the packed table searchable without sorting or alignment, requiring at most 8 clock cycles for alignment to cover all starting offsets in a 64-row array. A cross-column two-level asynchronous search conditionally gates the evaluation of the rule suffix upon a prefix hit, reducing unnecessary match-line switching activity. Fabricated in 28-nm CMOS, the chip achieves 430 MHz operation, supports up to 128-bit search width, and achieves a minimum search energy of 0.72 fJ/bit.
The memory wall due to data movement is a major challenge that limits performance and energy efficiency in bitwise-operation-intensive applications. To address this issue, this paper proposes a global merged reference-based magnetic random-access memory (MRAM) logic-in-memory structure. The proposed structure generates operation-specific reference resistances by controlling the effective parallelism of the reference bitlines (Ref-BLs) while maintaining the initial reference-cell configuration, thereby supporting memory read and two-input AND/OR operations without rewriting the reference cells or using dedicated AND/OR logic blocks. A read-disturbance-free scheme is also applied to protect the frequently accessed reference cells. A 32-kb test chip fabricated in a 28-nm FD-SOI process achieved sensing yields of 100%, 98.63%, and 99.73% and normalized energies per bit of 0.97×, 0.54×, and 0.49× relative to conventional MRAM for memory read, OR, and AND operations, respectively. Full-system evaluations achieved speedups of 2.23×–2.50× and 3.14×–4.97×, with normalized dynamic energy consumption of 0.39×–0.44× and 0.23×–0.30×, for bitmap-index queries and bitmap-based breadth-first search, respectively.
This letter presents a 2.8-GHz low-power CMOS low-noise amplifier (LNA) with an embedded self-mixing power detector (PD) for low-overhead RF power monitoring. The detector reuses two existing LNA node voltages as the signal and local oscillator (LO) inputs for direct down-conversion mixing, which avoids a dedicated LO generator, coupler, or standalone detector path. Implemented in a 65-nm CMOS process and operated from a 1-V supply, the prototype consumes a total of 400 μW, including 375 μW for the LNA and 25 μW for the PD. Measurements show an S21 of 14.5 dB, S11 of −12.9 dB, noise figure of 4.5 dB, IIP3 of −7.5 dBm, and input-referred 1-dB compression point (P1dB) of −17.5 dBm at 2.8 GHz. The embedded PD provides a monotonic output response over more than 20 dB input range while occupying only 0.012 mm2. The proposed architecture enables compact RF power sensing for adaptive low-power receivers, including interference-resilient front-ends with frequency-selective limiters.
A resistor-less 7-bit source-series-termination (SST) DAC-based transmitter (TX) with an 8-tap feedforward equalizer (FFE) is presented. Three different resistor-less SST segments (SSTSs) are employed to achieve low capacitance, compact area, and scaling friendliness. To reduce the output jitter of 4:1 multiplexer due to the inter-symbol-interference (ISI), the dual-feedback equalizer (DFEQ) is proposed. This TX is fabricated in 28-nm CMOS and has a maximum output swing of 1.1 Vppd. For the 112-Gb/s PAM-4 and 168-Gb/s PAM-8 data, the calculated energy efficiency is 1.59 pJ/b and 1.06 pJ/b, respectively.
