This article presents a 9.7-to-40.7-GHz ultra-compact dual-mode frequency multiplier (FM) capable of operating in both $\times 1$ and $\times 2$ modes, relaxing the required fractional bandwidth (FBW) and center frequency of the local oscillator (LO) in broadband digital beamforming systems. A novel magnetic-decoupled reconfigurable (MDR) transformer (XFMR) is proposed to realize ripple-invariant band shifting and output multiplexing, enabling full coverage of Ku-, $K$ -, and Ka-bands within a compact floorplan. An intuitive design methodology of the MDR XFMR is detailed to demonstrate its capability for concurrent multi-band optimization. Moreover, a new input-reused push-push (IRPP) topology is introduced to achieve simultaneous signal amplification and frequency doubling. By sharing the input stage, the proposed active core improves area efficiency and reduces input return loss across a large frequency span. Fabricated in 65-nm bulk CMOS, the prototype achieves a measured FBW of 123% with only a chip area of 0.24 mm2. The output power of 6.5 dBm is delivered with a variation of 2.2 dB from 9.7 to 40.7 GHz. In frequency- $\times 2$ mode, the measured fundamental rejection ratio exceeds 31 dBc, and the drain efficiency reaches 4.5%.
As high-bandwidth memory (HBM) performance continues to increase, buffer-die logic integrates increasingly diverse control, reliability, and test functions within a limited area budget. Therefore, reducing the hardware overhead of test-support logic is an important design consideration. Conventional logic built-in self-test (LBIST) uses standalone pseudo-random pattern generator (PRPG) and multiple-input signature register (MISR) blocks for pattern generation and response compaction, adding dedicated test hardware. This article proposes a self-test architecture for buffer-die in HBM based on error correction code (ECC) reuse. In particular, by exploiting the fact that the native system ECC (S-ECC) in HBM operates through cyclic redundancy check (CRC), the S-ECC is repurposed as the PRPG and MISR. A pre-test verification procedure is also introduced to validate the reused ECC before it is used as an on-chip test resource. Experimental results show that the proposed serial and parallel S-ECCs achieve 5.6% and 4.23% reductions in test-support hardware area, respectively, while maintaining comparable test effectiveness and test cost compared with conventional LBIST. These results demonstrate that S-ECC reuse provides an area-efficient LBIST architecture for HBM3 buffer-die logic while maintaining comparable test capability and test cost.
In biological neural systems, heterogeneous neurons rarely operate in isolation; their interactions via passive couplings are fundamental to information processing. Yet existing hardware demonstrations of the Smale paradox have been confined to homogeneous neuron pairs. This paper experimentally and theoretically demonstrates a heterogeneous Smale paradox: two distinct resting memristive neurons, a locally-active memristor (LAM) neuron and a Chua corsage memristor (CCM) neuron, both poised at the edge of chaos, become collectively activated into periodic spiking when coupled via a resistor acting as an artificial electrical synapse. As the coupling resistance increases, the system further transitions into bursting. Theoretical stability analysis, fast-slow decomposition, and hardware experiments validate all predicted regimes. The results reveal that intrinsic time-scale separation and passive coupling alone can generate rich neural firing patterns, offering a compact, bio-plausible building block for neuromorphic computing.
This paper proposes an RF energy harvesting system capable of operating over a wide input power range. The system incorporates a reconfigurable rectifier with a proposed digital gate-bias relocation technique to enhance power conversion efficiency under high input power conditions. The rectifier configuration and gate-bias tuning are jointly managed by a dual-parameter maximum power point tracking (DMPPT) controller, enabling efficient operation across a broad input range. Furthermore, the rectifier output feeds a load-modulation and dynamic voltage-regulation unit that functions as a variable load, adjusting the system output voltage in response to input power variations and thereby facilitating MPPT. A tunable matching network is also employed to maintain proper impedance matching under both high- and low-power scenarios. In addition, a pipeline startup scheme is introduced to accelerate the system startup time. Experimental results demonstrate that the proposed RF energy harvesting system achieves a 15-dB high efficiency input power range and a peak efficiency of 32.5% at 0 dBm.
Voltage-controlled magnetic anisotropy (VCMA) magnetic random-access memory (MRAM) enables sub-nanosecond voltage-driven switching, yet its readout remains challenging. This paper presents a 512-Kb VCMA-MRAM macro that overcomes the readout limitations of high-resistance magnetic tunnel junctions (MTJs), including reduced sensing margin and increased read latency caused by limited read current. The macro incorporates a reference-shared capacitive-coupled sense amplifier (RS-CCSA) that uses a P-state-referenced sensing baseline and capacitive coupling to enlarge the voltage-domain decision margin without increasing the read current. A retained-state burst readout scheme reuses the sampled reference baseline and sensing state across consecutive accesses to reduce repeated initialization overhead and accelerate continuous readout. For process, voltage, and temperature (PVT) robustness, digitally controlled trip-point trimming restores the sensing decision window, while a write–read–match-based burst timing adaptation method verifies burst-read correctness and selects the shortest safe interval. Designed in a 28nm CMOS technology, the proposed macro achieves a 438.5mV sensing margin, 1.73 ns normal read latency, and 52.63 fJ/bit read energy, while maintaining reliable readout down to 0.6V. Row-oriented burst operation further reduces the average read latency and energy to 1.12 ns/bit and 14.25 fJ/bit, respectively.
