A single-channel 12 GS/s 7 b time-domain analog-to-digital converter (ADC) in 28nm CMOS is presented. The proposed ADC inserts a programmable PVT-robust time-difference amplifier (TA) between pipeline SAR-TDC stages and separates coarse and fine stage delay implementations, enabling simultaneous optimization of speed and time resolution (TLSB). Furthermore, a self-adaptive TA calibration is proposed to align the TLSB of the coarse and fine stages. The ADC consumes 52.9 mW and achieves 34.9-dB SNDR and 44.9-dB SFDR for Nyquist inputs with only occupying 0.0035mm2. The small input capacitance of the VTC allows an effective resolution bandwidth (ERBW) exceeding 16.16 GHz.
This paper presents a dual-mode burst-mode receiver (BMRX) in 28-nm CMOS. A pipelined feedforward equalizer (FFE) achieves higher summer bandwidth and extended summing time margin with 9 taps. Moreover, the successive approximation register (SAR) based auto gain control (AGC) logic and data reference level (dLev) estimation technique are incorporated to provide a fast and robust adaptation process across a wide range of received optical power (ROP), achieving 6.4-ns amplitude settling time and 10.9-ns phase locking time. This work demonstrates the first 50-Gbaud non-return-to-zero (NRZ)/PAM-4 BMRX with near 1/10th the power and area compared to digital signal processing (DSP)-based solutions, achieving the highest sensitivity of −26dBm/−16dBm in mixed-signal schemes.
