Today’s explosively growing data volumes and the high storage cost make compression crucial for the Big Data industry. Deflate is a widely used lossless compression format that incorporates the LZ77 algorithm, which replaces repeated character strings with pairs, and the Huffman algorithm, which recodes characters based on their frequency of occurrence. The decoding process for a deflate-encoded file is called inflate. The decompression speed is critical, as stored data are typically compressed once but repeatedly decompressed for use in data processing systems. Consequently, strategies have been developed to enhance the decompression speed of inflate. The main challenge in improving inflate throughput lies in the data dependencies that invalidate parallel operations in Huffman decoding. Some studies [1], [2] have modified the deflate format to eliminate these data dependencies and achieve parallelism, but this approach results in incompatibility with existing inflate implementations. A speculative Huffman decoder for the GZIP decompressor, as proposed in [3], improves parallelism, resulting in a 69% increase in throughput. However, a single index checkpoint cannot ensure the success of the speculative thread (ST), which affects inflate throughput. Additionally, the ST stops when it encounters an end-of-block (EOB) marker and only restarts after the primary thread (PT) meets an EOB, limiting the ST’s efficiency. When Huffman decoding is accelerated, the throughput of the LZ77 decoder may become the critical path. The LZ77 decoder can be parallelized using a two-pass method. Other approaches [4], [5] cyclically partition the history buffer to access multiple memory locations simultaneously.
The increasing demand for low power edge-Al devices that target various tasks has driven many research efforts. To address this demand, many technologies such as computing-in-memory (CIM) [1], spiking neural networks (SNN) [2], and asynchronous logic [3] have been implemented on edge-Al devices. However, previous works either had energy consumptions of many mW [1, 2, 3, 5] or exclusively addressed a single task [4]. In this paper, we propose a neuromorphic processor (ANVMP) that adapts non-volatile memory (NVM)-based CIM, asynchronous logic and achieves the performance of $52.6~ \mu \text{W} 1.25 \text{pJ} / \text{SOP} \text{@} 0.55 ~\text{V}, 10 \%$ event rate, and $0.7 \%$ activation ratio (Fig. 1 (top)). The energy-efficient NVM-based CIM allows to power off the CIM macros completely during idle time to save power. The SNN-based neuromorphic computing uses binary coding which removes the need for DACs for CIM processing, and sparse spikes which reduce the energy consumption of information transmission with the cost of throughput. The event-driven nature of asynchronous logic allows energy to go where and when needed. Moreover, asynchronous logic offers fine-grained controls of CIM macros, which saves its power-on time.
The emergence of 3D-stacking in semiconductor technology has revolutionized CIS chip design, offering enhanced performance and efficiency in a smaller form factor. Pulse-width modulation (PWM) pixels are favored for stacking due to the time-domain output with immunity to interconnection impedance and downstream noise. Recent research simplified comparator designs, enabling the integration of all pixel devices into stacked chips. However, in the latest 3-layer wafer stacking processes, the intermediate layer can only accommodate NMOS design, posing a challenge for achieving an NMOS-only PWM pixel circuit. Current research on PWM pixel circuits mainly focuses on two types of architecture. The first type, proposed in [1–2], employs a common source as the in-pixel comparator, enabling a high-gain output at low voltages, however, requiring the use of PMOS. Moreover, the voltage gain, which depends on the input signal, may affect the circuit linearity. The second type, proposed in [3–5], uses NMOS as a switch, benefiting from using only NMOS components. However, the conductivity of an NMOS switch also depends on the threshold voltage and body effect, leading to signal-dependent variations which impact the overall linearity. Thus, mitigating the body effect is crucial for achieving high linearity. In this work, in-pixel voltage-to-time conversion is achieved by using only three NMOS devices, while the influence of body effect on the linear response is addressed through the proposed differential comparison technique.
Monitoring our multi-biological signals (bio-signals) provides us with a holistic view of our physiological condition (Figure 1). With increasing demand for integrating multiple bio-signals into a single chip, it is imperative to address multiple design challenges for efficient multi-modal biosensor acquisition [1]. The bio-signals include bio-potential signals (ExG), photo-plethysmography signals (PPG), and bio-impedance signals (BioZ) that are all unique in their electric properties (voltage, current, and resistance), have a large dynamic range ($4 \times$ order magnitudes in frequency and amplitude), and have a tremendous amount of variation among channels (middle of the Figure 1). The challenge of amplifying and quantizing diverse in-band bio-signals with a single signal acquisition circuit has attracted significant attention among researchers [2–6].
Recently, significant progress has been achieved in low-power keyword spotting (KWS) ASICs, which can serve as always-on wake-up function blocks for computationally intensive speech processing tasks. A 3-class CNN based KWS classifier consumed 510 nW power without including on-chip ADCs [1]. In [2], an ultra-low power event-driven level-crossing (LC) ADC was employed, reducing standby power to 148 nW. However, LC-ADC is vulnerable to DC drift. Other works include a 12-class KWS chip consuming $23 \mu \mathrm{~W}$ power [3], and a skip RNN-based 7-class KWS chip consuming 1.5 $\mu \mathrm{W}$ power [4]. Despite these technological advancements, researchers are still seeking KWS solutions with even lower power consumption, while not compromising on other key specifications such as keyword variety, classification accuracy and latency.
