Microfluidics is a rapidly growing field that aims to simplify complex analytical procedures by moving them to small-scale devices. A particularly interesting application of microfluidics are so-called Organs-on-Chips, i.e., microfluidic devices that mimic the structure and function of human organs and, therefore, allow studying the effects of drugs and diseases. Recent recognition of the need for standardization in this domain has led to the generation and uptake of new ISO standards—providing the basis of modular and reusable microfluidic building blocks that allow for various organ-on-chip setups. However, designing these building blocks, especially so-called routing blocks that interconnect pumps, cell cultures, and other modules is a cumbersome, repetitive task that is still conducted manually. In this work, we propose a design and routing method that significantly simplifies the design of such routing blocks by fully automating the process of interconnecting components of a microfluidic chip. The evaluation of physical, fabricated routing blocks that were designed using the proposed method showcases its feasibility in real-world applications and its potential to reduce design effort and time significantly. In order to make the work accessible to the microfluidic community, we provide implementations of the resulting methods in the form of a user-friendly, interactive online tool, provided as part of the Munich Microfluidic Toolkit (MMFT).
Homomorphic Encryption (HE) provides strong privacy guarantees by enabling computation directly on encrypted data, but at the cost of substantial computational overhead. Despite recent advances in algorithms and hardware, a gap remains between theoretical feasibility and practical deployment. To close this gap, we advocate a new encrypted computing paradigm that integrates application-level insights with ciphertext encoding to maximize Single-Instruction-Multiple-Data (SIMD) efficiency. Specifically, it comprises (1) pattern-aware encoding along the dominant reduction axes to reduce rotations, (2) Interleaved Assembling to re-densify ciphertexts after dimension reductions, and (3) encryption-aware Rot-structural pruning to exploit weight sparsity in accelerating encrypted neural network computation. On GPUs, it achieves speedups of up to 191× (Cora), 96× (Citeseer), 27× (Pubmed), on graph neural networks (GNNs) and 7.8–27.6× (MNIST and CIFAR-10) on convolutional neural networks (CNNs) such as LeNet, VGG5, ResNet20, all without accuracy loss. We conclude with an outlook on extending this design to large language models and beyond.
Advancing technology nodes have significantly increased the complexity of transistor sizing in analog circuit design. Although artificial intelligence (AI) techniques show potential, their lack of integrated domain expertise often leads to slow convergence in practical applications. We propose ASTRA (Automatic Sizing of Transistors with Reasoning Agents), a novel optimization framework that implements the Model Context Protocol (MCP) to create structured reasoning pathways between Large Language Models (LLMs), domain knowledge bases, and Bayesian Optimization (BO). ASTRA introduces a two-stage process: first, MCP-guided design initialization that leverages Retrieval-Augmented Generation (RAG) to quickly identify feasible regions using gm/ID methodology; and second, BO-based optimization focused on critical transistors, identified through LLM reasoning with data-driven validation. A key innovation of ASTRA is its ability to seamlessly integrate with and enhance virtually any existing transistor sizing algorithm at minimal additional cost. Unlike purely data-driven or black-box LLM approaches, ASTRA maintains traceable decision processes that can be verified and refined. Evaluated on three real-world analog circuits, ASTRA enhances multiple classical optimization methods, achieving up to 4.35× fewer simulation iterations and 2.36× performance improvements, demonstrating its effectiveness as a general open-source framework for advancing analog circuit sizing. 1
