Abstract With the continuous scaling down of the Integrated Circuits process, the issue of single-event transient in FinFET technology has become increasingly crucial. In this study, 3D models of inverters based on FinFET technology are established through TCAD simulation. By simulating the single-event transient of inverter units under various driving capabilities, the study quantitatively determines the impact of driving capability on SET pulse width. Additionally, the study delves into the underlying mechanism behind this relationship, focusing on the charge collection mechanism. The simulation findings indicate that increasing the driving capability leads to a higher recovery current and reduced SET pulse width. These results provide valuable insights for cost-effective mitigation strategies against single-event transient in advanced FinFET technology.

This paper presents a simulation study on the single-event transient (SET) radiation response and influencing factors of FinFET device and compares the charge collection under different processes. Based on TCAD simulation, a physical model of a bulk FinFET device was established to investigate the effect of drain bias voltage on the charge collection mechanism for different Linear Energy Transfer (LET) values of incident heavy ions. The results indicate that at low LET, the tendency to increase charge collection and heavy-ion-induced current peak in the FinFET device is more pronounced due to the competition between the drift mechanism and the parasitic bipolar amplification effect on the drain-side charge collection. Additionally, the study compared the radiation-induced currents of FinFET, FDSOI and planar bulk CMOS device. The findings demonstrate that the charge collection of the FinFET device is smaller than that of planar bulk device but larger than FDSOI device, with the difference being more significant at high LET.

This article mainly focuses on the single event function interruption (SEFI) of 40 nm monolithic resistance random access memory (RRAM). Three dynamic modes were used in the experiment, including two read-only modes and write-read-read mode. The SEFI cross-section of three dynamic modes are similar. SEFI observed in the experiment is further divided into several types according to the characteristics of the error. The basic mechanisms of the different types of SEFI are analyzed and explained accordingly.

Integrated circuit (IC) devices play unique role in the field of aerospace technology applications. This chapter introduces the space radiation environment and radiation effect sensitivity of common orbits of current spacecrafts. The radiation effects of space radiation on microelectronics devices are discussed and radiation hardening technology and radiation test evaluation technology for integrated circuits are described. The conventional simulation methods of Integrated Circuit radiation effects are also addressed.

This paper uses 3D TCAD simulation tool to study the single event transient (SET) characteristics of four types of logic cells (INVX2, NAND, NOR, INV_STACK) with nano-scale FDSOI CMOS process, and the influence of the LET value on the SET pulse width characteristics of the four cells. Simulation shows that when heavy ions strike NMOS, among the four cells, the NAND structure introduces the smallest amplitude and pulse width, while the NOR structure introduces the largest amplitude and pulse width. On the other hand, when PMOS is stricken, we got opposite results. In both cases, the INV_STACK structure has advantage in SET minimization. Based on the simulation results, it is indicated that the SET amplitude and pulse width of the four logic cells all increase with the LET value, while the increase rates decline with LET.

基于28 nm体硅CMOS工艺,设计了双路滤波的触发器(flip-flop,FF)结构,在传统的双互锁存(dual interlocked cell,DICE)加固基础上,对数据、时钟及复位信号均引入双路滤波结构.为研究不同滤波宽度的加固效果,设计了不同的滤波梯度.试验结果表明:当LET值为13.1 MeV·cm2·mg-1的Cl离子和LET值为37.3 MeV·cm2·mg-1的Ge离子分别辐射时,对该加固触发器电路分别以不同滤波宽度对SET进行滤波,可完全抑制SEU,且滤波宽度越大,加固效果越显著.

We investigated the heavy ion single-event effect (SEE) susceptibility of 40nm monolithic resistance random access memory (RRAM). The results show that single-event upset (SEU) of the memory cell occurred only in the write operation. The SEU of the cell was caused by the single-event transient (SET) of the peripheral circuit and the selection transistor. The dominant SEE type in dynamic modes was single-event functional interruption (SEFI). Some SEFIs could revert on their own in the next cycle, the rest needed a power cycle. We classified and analyzed all SEFIs into different types according to the number of cycles (or recovery mode) and the address distribution of the error data. Different types of SEFI are caused by SEU in different registers.

This paper researched on the effect of different bias conditions on the data retention characteristics of 55nm SONOS flash at a high total dose of 200 Krad(Si). The results show that the degradation of SONOS flash data retention characteristics is the most serious under static bias condition. And the data error rate is positively correlated with read frequency. But overall, the total ionizing dose (TID) has little effect on the data retention characteristics of SONOS flash.

In this paper, the data retention capability of 55nm SONOS Flash under the worst condition is studied by superimposing experiments of program/erase cycles, total ionizing dose (TID) and data bake. The results show that after 100k program/erase cycles and data bake, the data retention of the memory transistor is basically not affected. After 100k program/erase cycles, 200Krad(Si) TID and data bake, the data retention of the SONOS memory transistor is mainly reflected in the radiation-induced charge leakage. If the data is rewritten after TID, irradiation has basically no impact on its data retention capability.

宇航抗辐射加固集成电路是航天工程的核心基础技术.长期以来,美欧等国家对抗辐射加固集成电路持续支持并严格禁运,宇航集成电路的发展和自主可控是我国向航天强国迈进的关键核心基础之一,受到国家的高度重视.本文总结了宇航抗辐射加固集成电路发展特点和我国发展现状,分析了未来宇航抗辐射加固集成电路的发展需求,探讨了未来需要重点关注的3个技术方向,即软加固的天算芯片、高压功率器件加固和单粒子效应仿真.

Using single event effect sensitivity evaluation test method and test system as well as pulsed laser simulation sources, the SEE sensitivity of High-Speed Serial Interface was experimentally researched. The test results show that the JESD204B high-speed serial transmitter has strong resistance to single-event upset(SEU). The single-event upset sensitive area map of the JESD204B high-speed serial transmitter was obtained through experiments. The single-event upset sensitive unit of the device was located, which provided guidance for the design of high-speed serial interface chips strengthened by radiation resistance.

A wideband low-jitter phase-locked loop (PLL) presented in this paper adopts the adaptive-bandwidth technique and a two-stage ring oscillator which can be used for multi-rate serial link transmitter application. The two-stage ring oscillator is used to provide a high output frequency with optimal jitter performance, and the adaptive bandwidth technique is applied to guarantee the stability of the loop. The PLL was fabricated in a 28nm CMOS process, and the core occupies 0.05mm 2 . The experiment results show that the PLL has good robustness over PVT variation. The adaptive bandwidth PLL can generate clock with frequency from 6GHz to lOGHz. The measured Peak-Peak jitter at lOGHz is 10ps when the supply noise under the 1% of itself.

Abstract This work proposed and discussed a serial JESD204B data receiver and conducted a single event effect test on it. The test is used to analyzed the Single Event Upset (SEU), single Event Latch-up (SEL) and Single Event Functional Interrupt (SEFI). The purpose of the test is to determine if single event effect caused the chip to crash or increase the on-track error rate. The results show that the circuit has a strong ability to resist Single event effect.

为解决纳米CMOS工艺下单粒子多节点翻转的问题,提出了一种加固存储单元(RH-12T).在Quatro-10T存储单元基础上对电路结构进行改进,使存“0”节点不受高能粒子入射的影响,敏感节点对的数目是晶体管双立互锁(DICE)存储单元的一半.基于敏感节点对分离和SET缩减原理,进行了加固存储单元版图设计.在相同设计方法下,该存储单元的敏感节点间距是DICE存储单元的3倍.抗SEU仿真结果表明,该存储单元具备单节点翻转全加固能力.全物理模型单粒子瞬态仿真结果表明,该存储单元的线性能量转移(LET)翻转阈值为DICE存储单元的2.8倍,能有效缓解单粒子多节点翻转的问题.

An adaptive-bandwidth phase-locked loop (PLL) presented in this paper is a multi-function, general purpose frequency synthesizer. Ultra-wide input and output ranges along with best-in-class jitter performance allow the PLL to be used for almost any clocking application. To reach wide output range and optimal jitter performance, adaptive bandwidth technique is applied to guarantee the stability of the loop. Furthermore, a fast-lock circuit is used to improve locking speed. The PLL is implemented in a 65nm CMOS process, while the core occupies 0.05mm2 and measurement results shows that the adaptive bandwidth PLL can generate clock with frequency from 200MHz to 1.6GHz. The measurement results also show good robustness of the PLL over temperature and supply voltage variation. The measured RMS jitters at 1.6GHz is less than 0.8ps when the supply noise under the 1% of itself. The fast-lock process lasts less than 3us, and the complete lock time is determined as 1000 input cycles.

以CMOS存储单元为研究对象,介绍了仿真在CMOS抗辐射加固集成电路单粒子效应机理及电路抗单粒子加固设计方面的研究进展,讨论了特征尺寸的缩小对单粒子辐射效应的影响,提出了利用交叉隔离和错误猝熄的方法改进传统存储单元的加固性能,并通过试验验证了该方法的有效性.

We investigated the total ionizing dose (TID) influence on the single-event multiple-cell upsets (MCUs) in 65-nm 6-T static random-access memory and found that MCU sensitivity of the device is enhanced by TID. MCU caused by particle strike in pMOSFET (p-hits) or nMOSFET (n-hits) is distinguished by the MCU pattern. Analysis of MCU pattern shows that both p-hits MCU and n-hits MCU are enhanced by TID, and they have different mechanisms. Enhancement of n-hits MCU is due to the positive threshold voltage shift ( $\Delta V$ th) of the pull-up pMOSFET, while p-hits MCU is strengthened by the increase in the equivalent resistance of p-well contacts caused by oxide-trapped charges (Not) trapped in the shallow trench isolation.

空间应用的集成电路受到辐射效应的影响,会出现瞬态干扰、数据翻转、性能退化、功能失效甚至彻底毁坏等问题.随着器件特征尺寸进入到100nm以下(以下简称纳米级),这些问题的多样性和复杂性进一步增加,单粒子效应成为集成电路在空间可靠性应用的主要问题,给集成电路的辐射效应评估和抗辐射加固带来了诸多挑战.本文以纳米级CMOS集成电路为研究对象,结合近年来国内外的主要技术进展,介绍研究团队在65 nm集成电路单粒子效应和加固技术方面的研究成果,包括首次提出的单粒子时域测试和分析方法、单粒子多节点翻转加固方法和单粒子瞬态加固方法等.

SET sensitivity of a 180 nm CMOS embedded LDO is studied by experiments and simulations. Different output responses for different block striking are observed and methods to mitigate each influence are given.