To solve the problem that existing elliptic curve cryptography scalar multipliers are difficult to balance flexibility and area efficiency,a scalar multiplier with high area efficiency based on bit reorganization fast modular reduction is designed.Firstly,according to the operation characteristics of elliptic curve scalar multiplication,a hardware multiplexing operation unit that can realize two operations of multiplication and modular inversion is designed to improve the utilization rate of hardware resources,and the Karatsuba-Ofman algorithm is used to improve the calculation performance.Secondly,a fast modular reduction algorithm based on bit reorganization is designed,and a hardware architecture supporting secp256k1,secp256r1 and SCA-256(SM2 standard recommended curve)fast modular reduction calculation is implemented.Finally,the scheduling of modular operations for point addition and point doubling is optimized to improve the utilization of multiplication and fast modular reduction,and reduce the number of cycles required for scalar multiplication calculations.The designed scalar multiplier requires 275 k equivalent gates in 55 nm CMOS technology,the scalar multiplication operation speed is 48 309 times/s,and the area-time product reaches 5.7.

This paper proposes a high-performance elliptic curve cryptographic processor for the widely used TLS1.3 protocol. The processor supports two types of elliptic curve with general modulus in prime field defined in TLS1.3 protocol. Firstly, by modifying the high-radix Montgomery algorithm, a modular multiplication unit is proposed,which supports less than 521-bit width operators. Secondly, a parallel scalar multiplier structure with dual-modular multipliers is proposed. Based on this structure, to make full use of the two modular multipliers, a series of point operation timing arrangement is proposed in Jacobian coordinate, which supports two types of elliptic curves, makes the utilization rate of the modular multiplication unit reach 100%, 95.4% and 86.5% under different types of point operations. Compared with the existing design, the scalar multiplier in this work has a less cycle cost and less time consumption, as well as stronger versatility and configurability with similar time-area products. Under TSMC 55 nm CMOS technology, the clock frequency reaches 454 MHz. The scalar multiplication cost 851K equivalent logic gates, and the calculation speed of Secp256r1 curve is 31 230 times/sec.

指出了电子信息类专业存在的三方面主要问题,即尚未切实树立"三全育人"的教育理念,在专业课程设置中没有捋顺显性课程与隐性课程之间的关系,对专业教师在课程思政建设方面的贡献缺少有效的评价手段.对此有针对性地提出了改革措施,即确定了电子信息类专业实施课程思政的总体指导思想,强化了基于课程思政的专业课程群建设,提出了具体的实施办法,采取了有效的保障措施和激励机制.经过实践探索,教学改革取得了良好的效果,希望以此和同行共同探讨,共同提高.

Aiming at the problem that the current hardware implementation architecture using ASIC is difficult to meet the flexibility requirements of different applications, a high-performance reconfigurable architecture for lightweight block cipher (HRALBC) is proposed. By analyzing 42 mainstream lightweight block cipher algorithms, the pattern features and combination features of the algorithm are extracted; The reconfigurable processing unit is designed based on the pattern feature results and combined feature results; The reconfigurable processing unit array is designed according to the algorithm mapping law, and then the overall architecture is designed. Map different types of algorithms to HRALBC, verify their functional correctness, and analyze the mapping results. The experimental results show that under TSMC 55 nm CMOS process, the working frequency of HRALBC can reach 429 MHz, and the total area is 1.23M equivalent gate (GE). For different cryptographic algorithms, the area efficiency can be up to 22.33 Gbit·s-1·MGE-1. Compared with the Anole, for PRESENT64/80, SPECK64/128 and SIMON64/128 algorithms, the utilization of reconfigurable units is increased by 16.67%, 16.67% and 13.89% respectively, and the area efficiency is increased by 66.64%, 66.64% and 11.04% respectively.

为提高白茶叶面积密度(leaf area density,LAD)的反演精度,以浙江省安吉县昆铜乡茶场的茶树为研究对象,利用无人机激光雷达和地基激光雷达对白茶茶树的冠层点云信息进行提取,对比几种常见的点云分割算法,选择效果最好的随机森林算法将提取的点云信息进行枝叶分离,并对冠层点云进行体元建模,探究白茶茶树最优体元和激光接触频率的相关性,采用冠层分析法分别对机载和地基数据绘制LAD曲线,通过盲区互补实现LAD的双源协同反演.结果表明,运用冠层分析法适用于估算灌木型白茶茶树的叶面积密度,机载点云数据和地基点云数据协同估算精度最高(R2=0.930～0.963),地基数据估算精度次之(R2=0.824～0.933),机载数据估算精度最低(R2=0.693～0.838).因此,机载和基地协同反演可以提升白茶茶树LAD的估算精度,进而为进一步研究灌木型作物的理化参数提供数据基础.

随着电子商务的飞速发展,信息安全的重要性日益剧增.密码技术在信息安全中可以确保数据在通信过程中的安全、保密、完整且不被篡改.诸如ECDSA等数字签名算法为安全电子商务提供了关键技术.ECDSA设计架构通常采用不同的多标量乘算法和单标量乘算法分别进行运算处理,从而导致计算复杂度提升.针对该问题,提出了一种面向ECDSA的低复杂度多标量乘算法,该算法采用取模法构建联合多基链算法,对不能同时被基底{2,3}整除的部分进行3x2y取模运算,对得到的余数进行预处理.与现有联合多基链算法采用的贪心法相比,所生产的基链长度减小,有效地降低了多标量乘法的计算复杂度.实验结果表明,在curve-P256曲线下多标量乘和单标量乘的复杂度分别降低了约9.84％～30.75％和3.88％～26.81％;在联合处理的情况下,复杂度至少降低了约16.65％;预计算点相较于wNAF和联合多基链算法减少了约25.00％.通过Python搭建模型,相较于现有算法至少提高了14.80％的运行速度.

针对高校电子信息类专业中存在的人才培养与社会需求脱节、学生实践动手能力不足、教师缺乏工程实践经验和普遍存在的重学术轻实践以及企业难以参与人才培养全过程的问题,结合新工科的建设要求,建立了校企协同育人的新模式、具有专业特色的人才培养新方案、实践教学的新平台和新体系以及企业参与评价的校企共赢的长效合作机制,并制定了具体的人才培养实施方案,在集成电路设计与集成系统和电子科学与技术两个专业进行了实践探索,取得了良好的效果.

为了研究TZM合金(Mo-0.5Ti-0.1Zr)填充层对钼镧钇合金电子束焊接性的影响,分析了焊接接头显微组织和力学性能.结果表明,钼镧钇合金直接电子束焊接接头焊后产生贯穿裂纹,而填加TZM合金后,实现了钼镧钇合金的有效焊接.Zr元素的加入降低了Mo的氧化物在晶界处的聚集程度,提高了晶界结合强度;接头各区域显微硬度不同,焊缝区显微硬度与母材相当,为270～290 HV,两侧热影响区显微硬度最低.添加TZM合金后,钼镧钇合金电子束焊接接头抗拉强度明显提高,拉伸断裂发生于焊缝区,为脆性沿晶断裂模式.

本文制备了不同掺杂浓度的多晶硅纳米薄膜,研究了掺杂浓度对多晶硅纳米薄膜压阻和电学修正特性的影响.利用低压化学气相淀积法制备了不同掺杂浓度的多晶硅纳米薄膜,掺杂浓度分别为1.0×1020 cm-3、2.0×1020 cm-3、4.1×1020 cm-3和7.1×1020 cm-3.利用应变系数测量装置对不同掺杂浓度多晶硅纳米薄膜的应变系数进行了测量;利用恒流源和万用表测量不同掺杂浓度多晶硅纳米薄膜的电学修正特性.实验结果表明:多晶硅纳米薄膜的应变系数与掺杂浓度有关,应变系数范围:33.38～38.41;利用电学方法能够修正多晶硅纳米薄膜的电阻,最大修正范围可达15.4％.多晶硅纳米薄膜具有较高的应变系数,适用于制作压阻式传感器;电学修正可用来调整多晶硅纳米薄膜的电阻,进而降低传感器的失调.

In order to facilitate the extraction of failure data, a failure database for mooring equipment of floating production storage and offloading ( FPSO) is designed.Through the failure mode and effects analysis ( FMEA) , the database of the basic data requirements is summed up.The conceptual structure model of failure database is established.At the same time, a series of data of the equipment failure mode, failure mechanism and failure cases for FPSO’ s mooring system are collected from the exist-ing domestic and foreign database.

随着EDA技术的发展，基于FPGA的系统设计方法已成为硬件设计的重要手段之一，FPGA课程教学在集成电路等电子类专业中所占据的地位越来越重要。针对这种实践性、应用性强的课程教学，文章从理论教学、实验教学和考核方式三方面入手，阐述了FPGA课程教学改革的方法。

To improve the energy efficiency of hydraulic excavators(HE),by analyzing the energy consumption of the hydraulic cylinders and motors in a standard working cycle,the importance of the research on the HE's rotation was proved.As the HE's rotatory system was taken as the research object,an energy-recover-and-reuse technology was introduced and a new hydraulic rotation system with high energy efficiency was put forward.Simulation was carried out with the Matlab software,the influence of the corresponding parameters on the HE's energy efficiency was obtained.And experiment was done to verify the simulation results,which have certain theoretical and practical value to the HE's energy saving research.

液压控制阀在液压传动系统中是对液压油液实现控制调节的元件,它使得液压系统可以进行操纵控制以完成一定的任务,因此在液压传动系统占有重要地位。在液压传动系统中液压控制阀的性能将直接影响到系统功能的实现。鉴于此,在本科液压传动课程的教学工作中开设了液压控制阀性能实验。文中对该实验进行了介绍,对实验中的主要性能参数进行了讨论,并通过对06级一个班同学随机调查的结果表明达到了开设本实验的目的。

液压泵和液压阀是液压系统中的关键液压元件,对它们的性能进行实验在液压传动课程的教学中非常重要,而液压泵/阀的性能测试实验台是进行教学实验的基础。该文介绍了哈尔滨工业大学研制的用于液压传动课程教学的液压泵/阀性能实验台,给出用实验台进行实验的基本原理和实验方法,从4个年级40个小班的实验效果来看,该实验台达到了设计要求,在实验教学中发挥了应有的作用。

The hydraulic pump is the device that converts mechanical energy into static pressure energy in hydraulic system. Its performance has direct influence on the performance of whole system. The test on its performance is a very important part in hydraulic transmission course. This experiment has been set in order to make the undergraduates enhance their understanding of the performance of hydraulic pumps and to let them master the experiment way of solving problems.The experiment aim, experiment device and its principle were introduced. The main performance parameters were discussed.To know the experimental effect, a random survey was made in the undergraduates who enters college in 2006.The results indicate that the expecting effect is achieved.

Dual fault-tolerance server is a good solution to guarantee the durative of servers' services and to enhance the reliability of ser-ver.Based on cluster technology,the hardware architecture of high-available dual fault-tolerance server is designed.Many software fault-tolerance methods are introduced into this platform such as self-check,heartbeat etc.And thus,a fault-tolerance management system running on this platform is realized.At last,availability of the fault-tolerance system is analyzed.