Zero-knowledge proof (ZKP), one of the most popular privacy-preserving schemes, enables the prover to convince the verifier of a certain statement’s correctness without leaking any private information. Among them, the Pairing-based succinct non-interactive argument of knowledge (zkSNARK), like Groth16 and Plonk, featuring succinct proof size and constant-time verification, is deployed across a promising ecosystem. However, the heavy operations of proof generation that grow rapidly with application sizes and the frequent verification that requires costly Pairing severely hinder broader adoption. Moreover, there are many other cryptographic schemes also constructed based on Pairing, such as Boneh–Lynn–Shacham (BLS) signature, functional encryption (FE), identity-based encryption (IBE), and so on. Unfortunately, existing synthesis-based ZKP accelerators suffer from low area efficiency and incomplete operator coverage, causing poor overall speedup and expensive deployment cost. This work presents the first silicon-proven crypto-processor that supports complete proof generation/verification phases and can adapt to other Pairing-based cryptography (PBC). To achieve high flexibility while maintaining cost efficiency, we employ holistic optimizations across algorithm, architecture, and compiler levels, including the hybrid-grained instruction set, dedicated memory system, reconfigurable datapath, custom Pairing compiler, and utilization-oriented timing scheduling. Fabricated in 28-nm CMOS, it covers all related operators and achieves a $6.4\times $ area reduction compared to prior synthesis-based work LegoZK, which currently makes it the most cost-effective candidate for the practical deployment of ZKP–PBC applications. As a case study, the processor performs $2^{16}$ -gate proof generation/verification with 0.15 J/0.11 mJ, offering two orders of magnitude energy savings over a 14-core 2.4-GHz CPU. For the Pairing operator, it achieves development agility to enable fast design space exploration. It delivers $17\times $ / $1.8\times $ improvements of area-time product (ATP)/energy compared to the prior ASIC work.

The development of quantum computing poses a serious threat to traditional cryptographic systems and has driven the rapid development of Post-Quantum Cryptography (PQC). Specialized hardware solutions, especially PQC chips, are considered a key to achieving secure and efficient migration of quantum cryptography. This review first introduces the relevant background and the main PQC schemes and then focuses on analyzing the design challenges and bottlenecks faced by the design of PQC chips. Next, the development status and unresolved issues of different technologies, such as Central Processing Unit (CPU) Instruction-Set Extension (ISE), Field-Programmable Gate Array (FPGA), Application-Specific Integrated Circuits (ASIC), and Domain-Specific Accelerators (DSA), are further organized and analyzed. Finally, on the basis of specific application requirements, the future development technology path of PQC chips is discussed.

White-box cryptography (WBC) seeks to protect secret keys (SKs) even under the white-box security model that features adversaries having full control of the execution environment. Due to the ever-growing demand for content protection under security-critical scenarios, the recent progress on WBC has been nothing short of spectacular. However, the security-prioritized strategy also brings massive computation overhead to the current dedicated white-box block cipher (DWBC), seriously hindering its broad application. Compared to traditional software-only solutions, this work proposes a highly efficient domain-specific and silicon-proven processor (named SiWB) to improve the throughput (energy efficiency) by hundreds (several orders) of magnitude. First, not only a standalone crypto-core in prior work, we develop a complete and robust system that integrates multiple hardware cores for accelerating DWBC, user-defined high-speed interface (UPIF) for improving data transmission speed and other synergetic components. Second, to enhance throughput while maintaining energy efficiency, we devise a multi-core architecture based on inter-core load-aware scheduling, ultimately achieving 11.4-Gb/s peak throughput and 14.2-Gb/s/W energy efficiency. Third, a configurable and area-efficient datapath supporting multi-size random linear transformation (LT) and non-LT (NLT) is designed to reduce resource redundancy by means of algorithm-hardware co-optimization. To our best knowledge, this is the first 28-nm silicon-proven hardware accelerator for white-box block ciphers under black-box mode, which occupies 1.8-mm(2) area and achieves 800-MHz peak frequency at 0.9 V. It supports several white-box block ciphers including SPNbox-8/16/24/32, Yoroi-16/32, and white-box addition/rotation/XOR white-box addition/rotation/XOR (WARX), delivering 389x speedup on average versus software programs optimized with advanced encryption standard new instructions (AES-NIs) on a 14-core 3.4-GHz CPU. It enables WBC to be a viable solution for applications with stringent throughput requirements, such as streaming media commonly demanding several Gb/s.

Reducing the precision in post-training quantization can cause catastrophic accuracy loss in Deep Neural Networks, especially when compressing the activations. To address this problem, we present a novel adaptive-precision quantization (APQ) and accelerator design that achieves lossless activation compression by exploiting the inherent coding redundancy. Compared to existing APQ methods, this design can be generalized to implement asymmetric quantization, making it particularly suitable for activations. The accelerator offers a practical solution to mitigate the computational workload imbalance problem incurred by variable precision. A dual-precision quantization scheme further provides the flexibility to trade off accuracy and performance.

Fully homomorphic encryption (FHE) enables privacy-preserving machine learning (PPML) at the cost of intensive computational overhead, which necessitates the use of domain-specific accelerators. To achieve comprehensive support for leveled FHE, this article presents a reconfigurable multi-scheme FHE processor that supports both client-side encryption/decryption and server-side evaluation. First, a reconfigurable processing element (RPE) design for modular arithmetic and a reusable data generator for polynomial sampling are developed to support the various operations in FHE. Second, a configurable RPE array supporting polynomial operations and a decoupled automorphism unit (DAU) necessary for homomorphic rotations are proposed to accelerate the FHE primitives with complex dataflow. Finally, an on-chip data generation strategy and a cache-aware operation scheduling (CAOS) method are introduced to alleviate the memory bottleneck in the end-to-end execution of FHE applications. The chip is fabricated in a 28-nm process and tested with end-to-end execution. Targeting a lightweight parameter set with polynomial degree N=4096 at 128-bit security level, the proposed chip achieves 4.05 mu J per encryption on the client side and provides a throughput of 8.72 kHMul/s on the server side. In terms of the number theory transform (NTT) operation, the chip demonstrates the highest throughput and best area efficiency compared with state-of-the-art solutions.

Transformer models have achieved remarkable contextual comprehension capabilities in recent years, mainly thanks to the self-attention mechanism. As the input sentence becomes longer, the computation of the attention quadratically increases and becomes the bottleneck. The dynamic sparsity is a prevalent approach to alleviate this problem. However, existing sparse attention accelerators incur substantial redundant computations, reaching the performance limitation. They typically employ single-level sparse structure, supporting multiple or fine-grained N:M sparse patterns, which fails to accommodate the diverse sparse pattern with low hardware overhead. By re-examining the distribution of sparsity patterns, we observe that more high-level sparsity exists across multi-level and within each level with negligible hardware overhead. With multi-levels, more hierarchical sparsity patterns can be exploited without increasing the tile size. Within each level, we further prune redundant elements in an NM-aware manner that fits sparsity patterns dynamically with global information. Motivated by the observation, this paper proposes AMS, an efficient Attention accelerator with Dynamic Multi-level Structured Sparsity. AMS exploits structured sparsity patterns using dynamic multi-level structure in a small tile size, resulting in both high sparsity and low hardware overhead. These structured patterns enable a coordinated optimization of both scheduling and compute array. Compared to DynaX, SOFA, Highlight, STA, and RTSA, AMS achieves speedups of 1.7×, 2.6×, 3.8×, 2.3×, and 16.1×, with power-efficiency gains of 1.6×, 2.4×, and 6.3× over DynaX, SOFA, and Highlight. Compared to V100, A100, and DFSS, AMS achieves speedups of 6.7×, 2.1×, and 1.3×, and power-efficiency gains of 35.2×, 18.1×, and 11.3×.

This 0.046mm(2) SHA-3 engine demonstrates overheads of only 17% area, 27% energy, and 0% latency while achieving provable glitch- and transition-robust security (power/EM TVLA MTD>100M). Glitch-free DPL reduces masked states by 3x, resulting in a 72,950 mu m(2) register area reduction and lower logic energy. LMDPL refresh preserves secure asymmetric-share mapping. Masked transitions enable partial replacement of DPL with SRL, saving 50,852 mu m(2) in registers, precharge gates, and multiplexers.

This paper presents the first metastability-based true random number generator achieving Gb/s throughput, supported by a provable stochastic entropy model. The proposed staggered working point ensemble architecture employs four entropy source cores with deliberate offset staggering to ensure PVT-resilient operation without real-time tracking. A stochastic model characterizes the entropy generation dynamics, establishing a conservative min-entropy lower bound compliant with international standards such as NIST SP 800-90B and AIS-31. Fabricated in 28 nm CMOS, the proposed design achieves entropy throughput of 4064.5 Mbps at $997.6 \text{fJ} /$ entropy-bit (1.3 V) and 1462 Mbps at $324.1 \text{fJ} /$ entropy-bit $(0.9 \mathrm{V})$. Validation across 40 test chips confirms full compliance with NIST SP 800-90B and AIS-31 suites. The design maintains a min-entropy exceeding 0.77 after 168 hours aging, demonstrates resilience to 60 mVpp power-injection attacks, and achieves 10.08 mV metastable point drift tolerance, confirming robust high-entropy operation against PVT variations.

Logarithmic Number System (LNS) offers a more efficient quantization format than integer system for data in Large Language Models (LLMs), with inherently simple implementation for multiplication operations. However, the addition operation in LNS is relatively complex and difficult to balance between precision and hardware overhead. In this work, we observe that the input patterns of the computing units in the inference phase of LLMs exhibit highly skewed frequencies, resulting in non-uniform contributions to the final error. Based on this observation, we propose the Beyond Uniform Approximation (BUA) to enhance the efficiency of LNS additions. From the perspective of Lookup Tables (LUTs), we propose LUT reshaping to efficiently reduce the approximation error, as well as LUT trimming, a heuristic method for simplifying LUTs within a given error budget. From the perspective of the entire LNS adder, we introduce auxiliary circuit approximation, which further reduces the hardware cost by simplifying computing data paths that are less frequently activated. Together, these techniques enable efficient approximate computing in LNS. Experimental results indicate that, compared to the Multiply-Accumulate (MAC) unit using the naive LNS adder, BUA significantly reduces perplexity across various LLMs while reducing Area-Delay Product (ADP) by 26.7% and Power-Delay Product (PDP) by 30.8%. Compared to the traditional integer MAC unit, LNS with BUA achieves higher zero-shot accuracy while reducing ADP by 35.1% and PDP by 44.0%. Moreover, we also offer additional approximation options that provide greater hardware savings with only minor degradation in accuracy.

This 0.046 mm2 SHA-3 engine demonstrates overheads of only 17% area, 27% energy, and 0% latency while achieving provable glitch- and transition-robust security (power/EM TVLA MTD $>100 \mathrm{M}$). Glitch-free DPL reduces masked states by $3 \times$, resulting in a $72,950 \mu \mathrm{m}^{2}$ register area reduction and lower logic energy. LMDPL refresh preserves secure asymmetric-share mapping. Masked transitions enable partial replacement of DPL with SRL, saving $50,852 \mu \mathrm{m}^{2}$ in registers, precharge gates, and multiplexers.

Coarse-grained reconfigurable arrays (CGRAs) have become prevailing to accelerate regular kernels coupled with a host processor. As the end-to-end applications are increasingly complex, it is necessary to consider mapping whole programs onto a monolithic CGRA, to avoid the bottleneck of host communication implied by Amdahl's law. State-of-the-art studies have developed compiling methods that spatially pipeline the whole program over hardware with many cores. However, these methods mainly focus on static reconfigurable dataflow architectures (RDAs) and fail to exploit the dynamic reconfiguration potential of dataflow architectures, resulting in suboptimal performance and underutilization of hardware resources. Nevertheless, it is nontrivial to generate a performant mapping on dynamic RDAs since instruction-level deadlocks are introduced. To address this challenge, this article proposes EDWAC, a whole-program compiler that generates high-quality configurations for dynamic RDAs. EDWAC resolves the deadlock problem by a two-stage deadlock-prevention mechanism, which comprises a shared-resource-constrained Place and Route (PnR) stage, and a finite state machine (FSM)-based resource reallocation stage. Together with a gated control flow intermediate representation (IR) design and throughput-oriented optimization methods, EDWAC achieves exceptional resource utilization and PnR feasibility.

As the semiconductor industry transitions into an era shaped by ubiquitous artificial intelligence,heterogeneous integration,and the prospective impact of cryptanalytically capable quantum computers,hardware security is increas-ingly extending beyond its traditional role as isolated crypto-graphic engines or standalone blocks[1,2].

Emerging 6G communication systems impose unprecedented requirements on cryptographic primitives, demanding ultra-high throughput, low latency, and strong resistance to implementation-level attacks. LOL2.0 is a recently proposed stream cipher framework that achieves high software efficiency and strong security in post-quantum settings. While several stream ciphers have been proposed to address performance demands, side-channel-protected hardware implementations capable of sustaining 6G-class throughput remain largely unexplored. In this work, we present the first side-channel-protected hardware implementation that meets the 6G-class throughput demand. Focusing on the LOL2.0 stream cipher framework, we leverage Time Sharing Masking to achieve first-order security under the glitch-extended probing model. This design realizes full-phase protection covering initialization, keystream generation, and tag generation. To address diverse deployment requirements, we design two masked architectures: a compact variant optimized for area and randomness efficiency, and a fast variant targeting the maximum achievable throughput. The proposed fast implementations achieve peak throughputs of 183 Gbps and 142 Gbps for the unmasked and masked configurations, respectively. Meanwhile, the compact architecture reduces hardware cost by achieving areas as low as 23.25 kGE and 141.98 kGE in unmasked and masked designs, respectively, while still maintaining competitive throughput. Security is validated through practical side-channel evaluations using Test Vector Leakage Assessment on FPGA platforms. Across up to 100 million measured power traces, no statistically significant first-order leakage is observed for any protected configuration. Overall, this work realizes side-channel-protected stream cipher hardware that sustains ultra-high throughput, providing a concrete path toward secure cryptographic deployment in future 6G communication systems.

We present SharpSAT, a heuristic-learning SAT accelerator that achieves fast solution times of 0.8 mu s for SAT and 16.1 mu s for UNSAT cases. Our design integrates: a fast clause learning unit that prunes the search space by deriving constraints from conflicts; a dual-BCP unit that accelerates implication propagation; and a heuristic variable decider introducing non-determinism to efficiently traverse the solution space. A 28nm prototype demonstrates 21.11x/2.61x (SAT/UNSAT) speedup over prior accelerators.

HAWK is the only lattice-based candidate in the second round of additional digital signature schemes of the NIST post-quantum cryptography (PQC) standardization process, which is characterized by its low latency, compact storage requirements, and floating-point-free computations. However, research on hardware implementations of HAWK has remained limited, due to its challenging hardware reuse across heterogeneous arithmetic operations and complex computation patterns. This lack of exploration in acceleration and deployment studies currently constrains its broader adoption in practical systems and the future standardization process. To address this issue, HawkPU is proposed, namely HAWK Processing Unit, an efficient and low-latency crypto-processor to accelerate HAWK signature generation and verification on FPGA. Our approach involves a novel vectorized strategy for NTT/FFT, and a high-throughput, reconfigurable arithmetic module that supports various types of integer operations. In addition, several optimized modules are also introduced, including a load-balanced data generation module, a compact GF(2) polynomial multiplier, and an optimized Golomb-Rice encoder/decoder. Furthermore, this paper presents the first full hardware accelerator for HAWK signature generation and verification, achieving a low-latency HAWK hardware implementation. Signature generation and verification performance in security level I are 22.2 μs and 45.2 μs on the Zynq-UltraScale+ platform. Compared to the state-ofthe- art design, our signature generation and verification speed on Zynq-7000 are 88.8x and 33.6x faster. The area-time products of signature generation and verification in terms of LUT/FF/DSP/BRAM are 41.6x/31.4x/51.3x/177.5x and 15.7x/11.9x/19.4x/67.1x lower than the previous work, respectively.

Dataflow-based coarse-grained reconfigurable architectures (CGRAs) and dynamic high-level synthesis (DHLS) are both promising for accelerating applications with nontrivial control and memory behavior, but existing compilation flows are typically fragmented and often struggle with control handling, memory ordering, and effective resource reuse. In particular, prior CGRA compilers are still limited in compiling control-rich programs, while existing DHLS flows are not well aligned with dataflow CGRA compilation. This paper presents RedPanda, a unified compilation frame work for both dataflow-based CGRAs and DHLS. The main contribution of RedPanda is a shared front- and middle-end built on a common RedPanda IR, which enables the two targets to reuse the same core compiler infrastructure. On top of this foundation, RedPanda introduces static analyses and transformations for branch handling, memory ordering, aggressive loop pipelining, and time-multiplexing-aware compilation, thereby improving support for control-/memory-irregular workloads while reducing unnecessary serialization and instruction overhead. After this shared compilation stage, the IR is lowered to target-specific back-end flows for CGRA mapping and DHLS circuit generation. Experimental results show that RedPanda reduces CGRA spatial execution cycles by 33.4%, improves temporal-CGRA resource efficiency by 37%, and reduces instruction count by about 13%. For HLS, RedPanda achieves at least 34% faster execution while using fewer LUT, DSP, and FF resources. These results demonstrate that RedPanda provides a practical unified compilation foundation for both CGRA and DHLS targets.

Boolean satisfiability (SAT) is a fundamental problem in formal verification and symbolic reasoning. In correctness-critical domains such as hardware verification and safety-critical systems, complete SAT solving is required to provide formal unsatisfiability guarantees. Boolean constraint propagation (BCP) dominates execution time in modern complete SAT solvers and is the primary performance bottleneck. This bottleneck arises because BCP is memory-bound and requires aggregating the states of many literals during clause evaluation. Such aggregation-centric access patterns incur substantial overhead in conventional digital implementations, while existing hardware accelerators either sacrifice solver completeness for throughput or preserve correctness with high logic and interconnect costs. To address these limitations, we propose HiPACS, a hierarchical mixed-signal in-memory architecture that accelerates BCP through analog charge-domain aggregation. HiPACS performs clause evaluation directly in memory, reducing data movement and digital reduction overhead. A hierarchical organization enables efficient and low-latency propagation using lightweight, low-resolution analog interfaces. To preserve solver completeness and correctness, HiPACS integrates a near-memory digital controller for decision making, backtracking, and conflict analysis, supporting both Davis–Putnam–Logemann–Loveland (DPLL) and Conflict-Driven Clause Learning (CDCL). On standard benchmarks, HiPACS achieves up to 665× speedup over Kissat on satisfiable instances and up to 8.6× over prior complete SAT accelerators, demonstrating the effectiveness and practicality of mixed-signal in-memory BCP for complete SAT acceleration.

Falcon is a lattice-based quantum-resistant digital signature scheme renowned for its high signature generation/verification speed and compact signature size. The scheme has been selected to be drafted in the third round of the post-quantum cryptography (PQC) standardization process due to its unique attributes and robust security features. Despite its strengths, there has been a lack of research on hardware acceleration, primarily due to its complex calculation flow and floating-point operations, which hinders its widespread adoption. To address this issue, we propose FalconSign, a high-performance, configurable crypto-processor designed to accelerate Falcon signature generation on FPGA/ASIC through algorithmhardware co-design. Our approach involves a new scheduling flow and architecture for Fast-Fourier Sampling to enhance computing unit reuse and reduce processing time. Additionally, we introduce several optimized modules, including configurable randomness generation units, parallel floating-point processing units, and an optimized SamplerZ module, to improve execution efficiency. Furthermore, this paper presents a finely optimized hardware accelerator for the Falcon scheme. Our FPGA implementation results demonstrate a throughput improvement of approximately 5.1 x compared to state-of-the-art designs, with 2.8x/4.5x/4.2x/3.2x fewer in the area (LUTs/FFs/DSPs/BRAMs)-time product, for NIST security level V. The crypto-processor occupies an area of 0.71 mm2 and achieves 5.2k OPS at throughput on the TSMC 28nm process for NIST security level I.

CPU simulators are vital for computer architecture research, primarily for estimating performance under different programs. This poses challenges for fast and accurate simulation of modern CPUs, especially in multi-core systems. Modern CPU peformance simulators such as GEM5 adopt the cycle-accurate and event-driven approach, which is timeconsuming to simulate the extensive microarchitectural behavior of a real benchmark running on out-of-order CPUs. Recently, machine leaning based approach has been proposed to improve simulation speed, but they are currently limited to estimating the cycles of basic blocks rather than the complete benchmark program. This paper introduces a novel ML-based CPU simulator named CAPSim, which uses an attention-based neural network performance predictor and instruction trace sampling method annotated with context. The attention mechanism effectively captures long-range influence within the instruction trace, emphasizing critical context information. This allows the model to improve performance prediction accuracy by focusing on important code instruction. CAPSim can predict the execution time of unseen benchmarks at a significantly fast speed compared with an accurate O3 simulator built with gem5. Our evaluation on a commercial Intel Xeon CPU demonstrates that CAPSim achieves a 2.2 - 8.3x speedup compared to using gem5 built simulator, which is superior to the cutting-edge deep learning approach