This letter presents a 3D-NAND-like Two-Transistor-One-Capacitor (2T1C) 3D-DRAM architecture, which features Indium-Gallium-Zinc-Oxide (IGZO) Vertical-Channel-Access-Transistors (VCAT), vertical bit-line (VBL) wiring and multi-deck stackable capability with back-end-of-line (BEOL) monolithic integration. The vertical IGZO channel, formed simultaneously by atomic layer deposition (ALD) in recessed sidewall cavity, ensures uniform performance across layers, circumventing the degradation associated with layer-by-layer processing and enabling low-bit-cost scaling. We experimentally validated a 2-layer 2T1C structure, characterizing the VCAT electrical properties, read/write operations characteristics, and a retention time of 15.7s. 3D-TCAD simulations further assessed the parasitic capacitance and sense margin of the 2T1C array, confirming the excellent potential of this 3D-DRAM architecture for ultra-high-density Gb-scale DRAM applications.

Computational spectrometers, which rely on reconstruction algorithms to decode spectral information from raw sensor data, are of potential use in portable, in-field spectrometry. However, research on such systems primarily focuses on the front-end encoding devices, and back-end decoding hardware remains limited by severe overheads. Here we report an in situ computational spectrometer implemented on a fully integrated 576-Kb memristor chip. With systematic robustness analysis, we develop memristive regularization and filter embedding strategies to overcome the extreme sensitivity of ill-posed spectral reconstruction, achieving software-equivalent accuracy. System-level benchmarking shows that our hardware takes only 125.0 ns to reconstruct one spectrum consuming 6.7 nJ of energy, which is 26.5 times faster and 162.7 times more energy-efficient than state-of-the-art computational spectrometers. Our work illustrates the potential of memristor-chip-based computational spectrometry and provides approaches for efficiently implementing signal processing algorithms on memristor chips.

Memristor-based convolutional neural network (CNN) accelerators have gained considerable attention due to their low latency and high energy efficiency, making them promising candidates for edge acceleration. Alongside statically stored model weights, dynamically generated intermediate feature maps during inference occupy a significant portion of the on-chip buffer capacity and directly affect the efficiency of hardware pipeline execution. However, there is a lack of theoretical analysis and methods for efficiently allocating on-chip buffer for feature map data. To address this gap, this article implements three innovative aspects. First, a mathematical model is developed to estimate the minimal buffer size required for pipelined inference of CNNs on memristor-based accelerators, offering accurate and swift evaluations of the buffer size requirement. Second, based on this model, the article establishes mathematical conditions for buffer requirements to maintain a blocking-free pipeline during CNN inference, providing theoretical guidance for on-chip buffer allocation strategies. Third, a simulation-in-loop optimization method is proposed to further reduce latency by efficiently increasing the buffer size of critical layers. To validate our proposed model and method, evaluations were conducted on five representative models: ResNet-18, ResNet-50, YOLO-v5, U-Net, and Faster-RCNN-FPN. The results reveal a remarkably low average estimation error of only 2.6% between the mathematical model and the experimentally measured results, with the maximum error still below 10%. Moreover, our simulation-in-loop optimization strategy achieved significant latency reductions ranging from 5.3% to 57.5% across the five models.

Resistive random-access memory (RRAM) has been extensively studied as a promising candidate for high-density computing-in-memory (CIM) applications, yet its multi-level cell (MLC) precision is fundamentally compromised by conductance relaxation-an intrinsic instability driven by spontaneous oxygen vacancy $(V_{\mathrm{O}})$ diffusion. This work demonstrates a pre-cycle induced relaxation suppression (PIRS) technique on a 40 nm 16 Kb RRAM macro to thermodynamically stabilize the conductive filaments (CFs). We elucidate that the pre-cycle operation refines the CFs into enhanced “hourglass” morphology, effectively pruning unstable conduction paths. Quantitative analysis using relative deviation (RD) and relaxation velocity $(v_{\text{relax}})$ metrics reveals that pre-cycle significantly mitigates relaxation effect, securing a robust 3-bit/cell MLC with superior thermal stability $\left(25-125^{\circ} \mathrm{C}\right)$. System-level benchmark across image classification (e.g., DeiT-Tiny) and reconstruction (e.g., CAE) tasks confirms that the proposed scheme suppresses the accuracy loss by $\sim 5 \times$ while improving the peak signal-to-noise ratio (PSNR) by up to $\mathbf{8 d B}$. This approach resolves a critical reliability bottleneck for future edge AI applications.

Edge AI urgently demand computing hardware with large on-chip storage capacity, low memory access overhead. Resistive random-access memory (RRAM) based digital computing-in-memory (DCIM) suits such scenarios by achieving a optimized performance balance in calculation precision, storage density and access overhead. However, traditional RRAM-DCIM scheme suffers from two issues: 1) RRAM multi-bit storage boosts density but introduces significant errors, while conventional ECC scheme requires massive redundant bits that offset density gains; 2) Wiring RC parasitism in large-scale arrays leads to slow and energy-intensive random access. To resolve these issues, the proposed computation-oriented DCIM (CO-DCIM) paradigm integrates two core solutions: a hierarchical multi-bit storage coding scheme and a charge-domain continuous access scheme. The designed CO-DCIM macro is fabricated in a 28nm CMOS technology. Measurement results show a single RRAM read latency of 2.5 ns, normalized read energy of 0.12 pJ/bit, and a storage density of 12.85 Mb/mm2. The macro is further evaluated on public SimpleAR-0.5B-RL and SimpleAR-1.5B-RL workloads, showing a 29.2x reduction in mapped-weight access energy relative to LPDDR5X DRAM at $256\times 256$ resolution.

In recent years, artificial intelligence (AI) has experienced rapid development, and high performance computing (HPC) has raised increasingly higher demands for hardware computational capacity. Resistive random-access memory (RRAM)-based computing-in-memory (CIM) technology is expected to overcome the bottleneck of memory wall and provide HPC solutions. However, CIM chips face critical thermal challenges, including severe hotspot formation and thermally induced performance degradation, due to increasing power density and strong data-space coupling effects. Existing thermal management solutions designed for conventional digital chips are not directly applicable to CIM architectures. In this work, we propose a comprehensive framework for thermal analysis and management tailored to CIM chips. Targeted strategies are developed across the design, pre-operation, and operation stages. During the design stage, it is essential to mitigate thermal-induced accuracy degradation by adopting optimized design strategies. During the pre-operation stage, we propose a latency-thermal co-optimization (LTCO) strategy for static thermal management. By combining LTCO with a genetic algorithm to optimize the neural network mapping scheme, we reduce the hotspot temperature by 6.5°C and the temperature standard deviation by 5.3°C, without increasing the latency. During the operation stage, we develop a dynamic thermal management (DTM) strategy tailored for RRAM-based CIM chips, considering their unique architecture and the coupling between data and space. The evaluation results show that when thermal management is triggered, the combination of LTCO and DTM achieves more than a 10

Memristor-based analogue computing in memory (CIM) offers revolutionary gains in energy efficiency and computing power for data-intensive applications such as artificial intelligence. However, it typically struggles with achieving high accuracy at the same time, owing to the noise-sensitive nature of analogue computing and the non-ideal characteristics at the device and circuit levels that inevitably result in computing errors. Although progress has been made in device engineering and hardware-algorithm co-optimization to mitigate the error and parasitic effects, many of these advances inadvertently incur a hardware or energy consumption overhead, undermining the core benefits of analogue CIM. This Review dissects the computing error sources across the CIM hierarchy from the memristor device and array to the system architecture and algorithm, and evaluates the strategies to minimize those errors. We highlight the material and device innovations, array-level techniques and algorithm-architecture co-design frameworks towards high-accuracy analogue CIM. By dissecting the trade-off between computing accuracy and implementation cost, this Review draws a roadmap for translating memristor-based analogue CIM technology from proof-of-concept prototypes to large-scale deployment for accelerating next-generation artificial intelligence.

As emerging nonvolatile memory, resistive random-access memory (RRAM) holds great promise as a cryogenic memory solution for quantum computing systems. Although device-level cryogenic performance has been previously investigated, the scalability of these observations to RRAM array remains unaddressed. In this work, we report for the first time the comprehensive electrical characterization of a 1024-device HfO2-based RRAM array from 300 K room temperature to 4 K Helium temperature. Forming voltages increase significantly, with mean value rising from 3.91 V at 300 K to 7.11 V at 4 K, while set and reset voltages exhibit minor increase with average set voltage from 1.30 V at 300 K to 1.46 V at 4 K and average reset voltage from 1.75 V at 300 K to 1.86 V at 4 K. Endurance test demonstrates robust performance over 1 M cycle without degradation at 300, 77, and 4 K, respectively. Most notably, retention and relaxation characteristics are dramatically enhanced at 77 and 4 K. The devices also exhibited strong immunity against read disturb across the investigated temperatures. These findings establish HfO2-based RRAM array as high-performance cryogenic nonvolatile memory, and pave the way for practical integration of RRAM array in cryogenic quantum computing circuits.

Here, we demonstrate the monolithic 3D integration of SOT-MRAM and RRAM on Si CMOS for the first time, namely M3D-SOT. The M3D-SOT prototype features a Si CMOS logic control layer for data input and output, an RRAM-based computing-in-memory (CIM) layer for feature extraction utilizing convolutional neural network (CNN), and an SOT-MRAM-based TCAM layer as attentional memory for storing and matching feature vectors. The chip’s bottom layer was fabricated with a standard 130 nm Si CMOS process, while the middle CIM layer and the top TCAM layer were manufactured using back-end-of-line (BEOL) compatible processes with temperature not exceeding 300℃. The M3D-SOT chip successfully executed a one-shot learning task using Omniglot dataset. The chip achieved a GPU-equivalent identification accuracy with approximately half the inferencing time and a 30× increase in energy efficiency. The study demonstrates the feasibility and significant potential of M3D-SOT chips for data-rich applications.

Reliability stands as a pivotal bottleneck for the commercialization of emerging nonvolatile memories, including resistive random access memory (RRAM). In this work, we successfully demonstrated a 40-nm HfOx-based RRAM chip featuring superior wafer-level uniformity and robust array-level reliability enabled by sidewall and interface engineering. A radical-enhanced annealing (REA) process was introduced to tackle the dry etching-induced reliability issues and enhance the control over the switching behavior of conductive filaments (CFs). With REA, we achieved 10.86 & times; larger ON/OFF ratio compared with the baseline without REA, along with 100k cycle endurance, ten-year retention at 85( degrees)C, and over 109 cycles read disturbance immunity. The characteristics of the RRAM chip's reliability and the mechanism for the impact of REA on the device performance were clarified in detail through extensive material characterization, structural simulation, and electrical testing. This work provides an effective scheme to address the reliability issue of RRAM and also promotes the large-scale integration of RRAM toward more advanced technology nodes.

In this work, we present a novel multi-bit programming scheme of 2T gain cell (GC), which effectively improves the current response linearity by biasing the read transistor in the saturation region. The high linearity significantly benefits the readout circuitry, especially the analog-to-digital conversion (ADC), and is also highly desired for computing-in-memory (CIM) or processing-in-memory (PIM) applications. Using the proposed programming scheme, we have successfully demonstrated 4-bit/cell capability in the fabricated InGaZnOx (IGZO) based 2T GCs. The output current of the read transistor exhibit a near-ideal linear relationship with the input voltage, achieving a R-squared (R2) value up to 0.9955. In contrast, the conventional programming scheme exhibits a much worse linearity with R2 ≈ 0.9070. Furthermore, the outstanding linearity of the proposed programming scheme can be retained over 80 seconds, while the multi-bit states become nearly indistinguishable for the conventional scheme.

We present the first 28nm hybrid compute-in-RRAM (CiR) accelerator for recommendation system (RecSys) based on the HYDAR framework: (1) DL ADCs enable early termination of non-Top-K calculations. (2) PPSP dataflow boosts throughput for irregular workloads. (3) A coarse-to-fine architecture preserves system recall accuracy. The 36M-RRAM CiR chip achieves 390K QPS with a SOTA 1574K QPS/W. The chips scale out to a 576M system for practical RecSys task, improving by 66x in QPS and 181x in QPS/W.

In this work, we present a $\mathbf{2 8 n m} \mathbf{1 6 M b}$ embedded resistive random-access memory (RRAM) IP, ideally suited for automotive over-the-air (OTA) update application. Our design features a 1T1R/2T2R hybrid array structure that enhances the reliability and system compatibility. To address the IR-drop issue and improve cell uniformity, a load balancing approach is implemented. A hierarchical column selection strategy is also employed to suppress the leakage current in the write path, optimizing write operations at high temperature. Furthermore, reliability test results demonstrate the RRAM IP achieves $\mathbf{1 0 0 K}$ cycles and 10 years of retention at $\mathbf{1 2 5}^{\boldsymbol{\circ}} \mathbf{C}$ in the 1T1R mode, and at least 200 K cycles and 10 years of retention at 125 °C in the 2T2R mode. These silicon test results pave the way for the application of RRAM in automotive OTA scenarios.

In this work, we present a novel multi-layer 2T0C DRAM architecture integrating lateral C-shape-channel FETs (LCCFETs) and vertical-double-gate FETs (VDGFETs) for high-density memory applications. The proposed structure employs LCCFET as the write transistor and VDGFET as the read transistor, with the LCCFET source connected to the VDGFET lateral gate (LG) and the VDGFET vertical gate (VG) enabling column access. Key innovations include a one-step ALD process for InGaZnO channel formation, ALD-based InZnO replace source/drain, and sidewall vertical-damascene TiN bitline for read transistors. The design supports n-layer parallel integration akin to 3D NAND, achieving an equivalent feature size of 8F2/n.

Present resistive random-access memory (RRAM)-based analog compute-in-memory (CIM) systems face significant precision and reliability degradation due to device variation and stuck-at-low-resistance (SALR) faults. We propose a one-weak-inversion-transistor-one-resistor (1-WIT-1-R) weight cell, which exploits weak-inversion readout of a conventional access transistor and synergistically leverages RRAM characteristics and circuit configurations to address these problems. By strategically operating the RRAM in reliable high conductance states (HCS) and optimizing the current-conductance (I-G) mapping, the 1-WIT-1-R cell suppresses weight variation and accelerates deployment. Moreover, its inherent current saturation characteristic immunizes computing channels against SALR faults, preserving inference accuracy. Compared to the conventional 1T1R cell, the proposed 1-WIT-1-R cell inherently reduces the relative deviation (RD) of weight current by 71.8% with a 1.59-fold programming speedup and demonstrates immunity to SALR-induced errors. The 1-WIT-1-R-based CIM array exhibits a 30-fold enhancement in SALR tolerance for image classification and sustains a high task success rate in robotic control tasks.

The iterative computation and probabilistic analysis of long-term time-series data struggle with noise accumulation, which degrades the signal-to-noise ratio and poses a bottleneck. Memristors fail to meet these demands due to the coupling between their switching and rectification mechanisms. Here, we introduce a silicon-compatible van der Waals ferroelectric memristor that decouples the rectification and switching mechanisms using a device architecture (Au/CuInP2S6/SiO2/Si), where the ferroelectric polarization of the two-dimensional CIPS layer governs the non-volatile resistive switching, while self-rectification is provided by an engineered Schottky barrier at the heterointerface. This decoupling enables the high on/off ratio (>105), high self-rectification (>108), and ultralow leakage current (<10−13 A), suppressing cumulative noise in sequential computations. We demonstrate the scalability and technological viability of this approach by fabricating a functional memristor array on a silicon-on-insulator (SOI) wafer with 100% yield and low device-to-device variation, highlighting its compatibility with mainstream silicon platforms.

We present the first 28nm hybrid compute-in-RRAM (CiR) accelerator for recommendation system (RecSys) based on the HYDAR framework: (1) DL ADCs enable early termination of non-Top-K calculations. (2) PPSP dataflow boosts throughput for irregular workloads. (3) A coarse-to-fine architecture preserves system recall accuracy. The 36M-RRAM CiR chip achieves 390K QPS with a SOTA 1574K QPS/W. The chips scale out to a 576M system for practical RecSys task, improving by 66x in QPS and 181x in QPS/W.

Analog computing-in-memory (CIM) based on resistive random-access memory (RRAM) faces critical challenges in achieving high-precision computing, primarily due to the relaxation effect and intrinsic noise. This work presents a co-optimization framework of programming and mapping schemes to address these challenges. We propose a progressive tolerance block programming (PTBP) scheme with a zigzag write sequence to accelerate programming and balance the relaxation behavior across the array. Furthermore, a noise-aware mapping (NAM) strategy is introduced to minimize the read noise by dynamically selecting more stable conductance states. The co-optimized framework demonstrates a 3.7× improvement in the conductance stability and reduces the error by one order of magnitude in a representative spectral reconstruction task. This work establishes a co-optimization methodology that extends the applications of analog RRAM-CIM toward noise-sensitive computing tasks.

Practical brain–computer interfaces should be able to decipher brain signals and dynamically adapt to brain fluctuations. This, however, requires a decoder capable of flexible updates with energy-efficient decoding capabilities. Here we report a neuromorphic and adaptive decoder for brain–computer interfaces, which is based on a 128k-cell memristor chip. Our approach features a hardware-efficient one-step memristor decoding strategy that allows the interface to achieve software-equivalent decoding performance. Furthermore, we show that the system can be used for the real-time control of a drone in four degrees of freedom. We also develop an interactive update framework that allows the memristor decoder and the changing brain signals to adapt to each other. We illustrate the capabilities of this co-evolution of the brain and memristor decoder over an extended interaction task involving ten participants, which leads to around 20