A moiré superlattice formed in twisted van der Waals bilayers has emerged as a new tuning knob for creating new electronic states in two-dimensional materials. Excitonic properties can also be altered drastically due to the presence of moiré potential. However, quantifying the moiré potential for excitons is nontrivial. By creating a large ensemble of MoSe2/MoS2 heterobilayers with a systematic variation of twist angles, we map out the minibands of interlayer and intralayer excitons as a function of twist angles, from which we determine the moiré potential for excitons. Surprisingly, the moiré potential depth for intralayer excitons is up to ∼130 meV, comparable to that for interlayer excitons. This result is markedly different from theoretical calculations based on density functional theory, which show an order of magnitude smaller moiré potential for intralayer excitons. The remarkably deep intralayer moiré potential is understood within the framework of structural reconstruction within the moiré unit cell.

Physically unclonable function (PUF) and true random number generator (TRNG) are the indispensable primitives for the Internet-of-Things (IoT) security. In this article, a highly robust unified PUF $/$ TRNG design is demonstrated. An entropy source (ES) chip based on 40-nm resistive random access memory (RRAM) is designed and fabricated, and a pseudo-forming technique is developed to ensure excellent robustness. The unified PUF $/$ TRNG is tested across $- 55\,\,^{\circ }\text{C}$ to 125 °C with different supply voltages, achieving < 0.001% bit error rate (BER) and >0.999 worst case min-entropy simultaneously. Excellent randomness is verified by NIST SP800-22 and 90B tests. This highly robust unified design can implement an authentication system with the authentication error rate (AER) approaching 0% and thus is promising for future IoT security applications.

A physically unclonable function (PUF) is a creditable and lightweight solution to the mistrust in billions of Internet of Things devices. Because of this remarkable importance, PUF need to be immune to multifarious attack means. Making the PUF concealable is considered an effective countermeasure but it is not feasible for existing PUF designs. The bottleneck is finding a reproducible randomness source that supports repeatable concealment and accurate recovery of the PUF data. In this work, we experimentally demonstrate a concealable PUF at the chip level with an integrated memristor array and peripherals. The correlated filamentary switching characteristic of the hafnium oxide (HfOx)-based memristor is used to achieve PUF concealment/recovery with SET/RESET operations efficiently. PUF recovery with a zero-bit error rate and remarkable attack resistance are achieved simultaneously with negligible circuit overhead. This concealable PUF provides a promising opportunity to build memristive hardware systems with effective security in the near future.

Homomorphic encryption (HE) is an encryption technology of which encryption and decryption process can be summarized as polynomials modulo multiplication computing with noise. In this paper, HE is firstly implemented on resistive random-access memory (RRAM) arrays, which are utilized as both matrix-vector multiplication (MVM) units and true random number generators (TRNG). Both high stability and good randomness are achieved for MVM and TRNG, respectively, by using different forming schemes, so that two distinct functions can be realized using the same device. Furthermore, the encryption-decryption process for privacy-preserving cloud computing is experimentally implemented on a hardware system with eight 144Kb RRAM arrays. For the whole RRAM array-based encryption-decryption process, small accuracy losses of 0.73% (for SVM) and 1.9% (for CNN) are achieved. This is the first demonstration of encryption computing acceleration with emerging device technology.

Physically unclonable function (PUF) has been increasingly used as a promising primitive for hardware security with a wide range of applications in the Internet of Things (IoT). In recent years, novel PUF techniques based on resistive switching mechanism in various emerging nonvolatile memories have demonstrated superior performance on reliability and integration density. In this work, a resistive random access memory (RRAM)-based PUF chip with 8-kb capacity is developed. Two operation modes, namely differential mode and median mode, are embedded on chip. To implement these modes, a current sampling-based sense amplifier is designed to distinguish the current values of the PUF cells and the reference cell. In addition, a split-resistance scheme is proposed to enhance the PUF's reliability significantly. The experiment results show that the differential PUF exhibits excellent performance with native bit error rate (N-BER) below 6 x 10(-6) and inter-Hamming distance (inter-HD) of 49.99%. In the meanwhile, the reconfigurability of PUF challenge-response pairs (CRPs) is demonstrated with 49.77% and 47.29% reconfigure-Hamming distance (reconfigure-HD) in the median mode and the differential mode, respectively.

A novel bi-functional memory-PUF module is proposed and experimental demonstrated using RRAM for the first time. The PUF mapping is generated utilizing the resistance distribution after successful forming. As different forming conditions have significant effect on the memory window of RRAM, a two-phase forming process is designed to generate and store the PUF information. Each RRAM can still be utilized as memory with program-verify technique, and PUF information can be read out directly by distinguishing resistance levels. The majority voting technique is applied to enhance the reliability. Less than 2% bit-error-rate is achieved across a wide temperature range from -40 to 125 °C by using 7 RRAM cells to represent one PUF bit. The 4 resistance levels remain distinguishable after 100-second baking at 125 °C, indicating excellent retention.

Resistive Random-Access Memory (RRAM) has been widely researched as a candidate of non-volatile memory, and also for application in hardware security in recent years. However, most of these applications only take advantage of certain evident features of RRAM (e.g. cycle-to-cycle or device-to-device variation), and can only implement a single function. In this paper, a novel data hiding technique is proposed to implement two different functions in normal RRAM devices that utilize the impact of Form resistance on the applied pulse number of SET process. The feasibility of this technique is experimentally demonstrated on a 1Kb RRAM chip, which is proved by hiding additional data in normal RRAM. The reliability of the proposed technique is further optimized using a multi-RRAM per bit method. The experimental results show that the optimized hidden data demonstrates nearly ideal Bit Error Rate (BER) with 8- RRAM per bit. The BER is below 3%, which can be maintained after more than 1000 cycles. In addition, this work also demonstrates that the data hiding technique has good temperature stability between -25 ○ C and 100 ○ C.

2D van der Waals ferroelectric semiconductors have emerged as an attractive building block with immense potential to provide multifunctionality in nanoelectronics. Although several accomplishments have been reported in ferroelectric resistive switching for out-of-plane 2D ferroelectrics down to the monolayer, a purely in-plane ferroelectric has not been experimentally validated at the monolayer thickness. Herein, a micrometer-size monolayer SnS is grown on mica by physical vapor deposition, and in-plane ferroelectric switching is demonstrated with a two-terminal device at room temperature (RT). SnS has been commonly regarded to exhibit the odd-even effect, where the centrosymmetry breaks only in the odd-number layers to exhibit ferroelectricity. Remarkably, however, a robust RT ferroelectricity exists in SnS below a critical thickness of 15 layers with both an odd and even number of layers. The lack of the odd-even effect probably originates from the interaction with the mica substrate, suggesting the possibility of controlling the stacking sequence of multilayer SnS, going beyond the limit of ferroelectricity in the monolayer. This work will pave the way for nanoscale ferroelectric applications based on SnS as a new platform for in-plane ferroelectrics.

A calibration-free and parallel-friendly RRAM TRNG utilizing the resistance perturbation is demonstrated and modeled for the first time. 128-parallel-output is experimentally demonstrated on a RRAM array, achieving the highest throughput of 230 Mbps. The switching asymmetry and nonlinearity of RRAM is fully utilized to enable the resistance to fluctuate in a stable range spontaneously. This unique calibration-free feature contributes to high entropy and excellent statistical randomness, which are verified by the NIST SP800-90B and NIST SP800-22 tests, respectively. Excellent reliability is also demonstrated under extreme temperatures ranging from -40°C to 125°C, 10% variation in the operating voltage, and continuous working. Finally, this high-performance TRNG is used to successfully implement a stochastic computing system for handwritten digits recognition, demonstrating the feasibility for edge computing application as well as low-weight and low-cost IoT applications.

Physically unclonable function (PUF) and true random number generator (TRNG) are critical primitives to provide lightweight hardware protection. As area is tightly restricted in IoT applications, merging PUF and TRNG is a novel trend to achieve higher area efficiency. In this work, a novel tri-functional module is proposed and experimental demonstrated using RRAM for the first time. A two-phase forming process is designed to generate and store PUF ID utilizing the impact of different forming conditions on the switching window. As PUF ID is stored by the switching window, instead of a fixed resistance, PUF cells can be written to low resistance state and high resistance state as usual, and can be used as memory and TRNG. The inter-Hamming distance of the generated PUF IDs approaches 0.5, and with the majority voting readout strategy, low BER can be achieved in a wide range of temperatures from -40°C to 125°C. TRNG produces the true random numbers based on the parity of the number of pulses consumed in a write-zero process. The generated random numbers are uniform and uncorrelated after XORed, and the statistical randomness is verified by NIST SP800-22 tests.

Memristors have recently been explored for hardware security applications such as true random number generators (TRNGs) and physical unclonable functions (PUFs). Several typical designs for memristor-based PUFs and TRNGs are summarized. PUFs are a novel hardware security primitive utilizing the intrinsic randomness of a physical system, and PUFs have broad potential applications in key protection and authentication. Unlike most conventional PUFs based on manufacturing variations, memristors have both manufacturing variations and intrinsic randomness in their resistance-switching mechanisms that can be utilized as entropy sources; for instance, device to device (D2D) variation and probabilistic switching behaviors. TRNGs are a cornerstone of hardware security and are widely used in secure chips and encryption protocols. Memristors have random telegraph noise (RTN) and cycle to cycle (C2C) variation characteristics that can be used for high-quality TRNGs. Here, research progress in memristor-based PUFs and TRNGs is reviewed, and how these sources of randomness are leveraged to generate security primitives is discussed.

A novel True Random Number Generator (TRNG) based on analog RRAM is developed. For the first time, the proposed TRNG harvests the variation of the pulse number in programming the analog states as the random source, and utilizes the parity of the pulse number to generate random bits. The TRNG throughput reaches >1 Mbit/sec for a single cell. The feasibility for chip-level parallel operation on multiple cells is verified experimentally to further improve the throughput. Excellent stability against temperature variation is also demonstrated. All the generated random bit streams pass the NIST tests across -40 to 125 °C. With an optimized small analog switching window, the endurance problem is significantly relieved as the functionality of TRNG is retained after 10 11 incremental switching cycles. Our high-speed and high-reliability TRNG design is compatible with the existing memory block and convenient for circuit implementation, making it suitable for future IoT applications.

Excitons in monolayer semiconductors have a large optical transition dipole for strong coupling with light. Interlayer excitons in heterobilayers feature a large electric dipole that enables strong coupling with an electric field and exciton-exciton interaction at the cost of a small optical dipole. We demonstrate the ability to create a new class of excitons in hetero- and homobilayers that combines advantages of monolayer and interlayer excitons, i.e., featuring both large optical and electric dipoles. These excitons consist of an electron confined in an individual layer, and a hole extended in both layers, where the carrier-species-dependent layer hybridization can be controlled through rotational, translational, band offset, and valley-spin degrees of freedom. We observe different species of layer-hybridized valley excitons, which can be used for realizing strongly interacting polaritonic gases and optical quantum controls of bidirectional interlayer carrier transfer.

Watermark is a very important technique for information security. In this work, a RRAM-based electronic watermark technique leveraging the impact of Forming conditions on Reset distribution is experimentally demonstrated. The Forming process is indispensable for almost all RRAM device. The Forming conditions can affect the shape and size of the conductance filament, and further affects the resistance distribution at Reset. The tested data shows that the stronger Forming condition can get smaller mean value of resistance, and the use of RRAM as memory is not affected. In this design, two different Forming conditions are used to write watermark data `0' and `1'. A resistance in parallel technique is applied to enhance reliability. The experimental results show that the bit error rate (BER) reduced from ~30% to ~7% after using the optimized method. And no reliability degradation occurs after 200 normal Reset/Set cycles.