In DC microgrids, conventional MOV-based solid-state circuit breakers (SSCBs) degrade under repetitive surge energy absorption, reducing clamping effectiveness and long-term reliability. This paper presents a thyristor-based bidirectional SSCB (TBCB) with an embedded symmetrical RCD snubber (ES-RCD). Two capacitors interchange functions between voltage clamping and current commutation according to the direction of energy flow, reducing component count and cost. The proposed TBCB eliminates MOV-related degradation, lowers peak thyristor voltage stress, and prevents surge current reflections. A 400V/4kW laboratory prototype demonstrates the TBCB’s reliable fault interruption, fast reclosing, and re-breaking capabilities. Experimental results validate the effectiveness of the proposed TBCB in enhancing the safety and robustness of DC microgrid systems.

Pulsed-power systems require solid-state switches that can simultaneously provide high blocking capability, strong pulse-current output, and practical system integration. However, suitable high-voltage thyristors for such applications remain limited, and conventional series thyristor stacks require increasingly complex multidrive schemes as the operating voltage rises. In this work, a scalable single-drive-controlled modular thyristor stack is developed using voltage-controlled thyristors and a capacitor-coupled drive topology. The fabricated stack extends the operating voltage from 1to 10kV with increasing stage count while retaining single-drive control, and achieves 10-kV/10-kA output in a seven-stage configuration. The proposed stack demonstrates the feasibility of a practical solution for pulsed power applications, as further illustrated by proof-of-concept experiments for high-energy ignition.

A scalable cyclically coupled hybrid (SCCH) DCDC converter is proposed for direct 48V-to-1V power delivery in data-center applications. The SCCH converter supports flexible multi-phase scalability, inherent current-sharing capability, and a sextuple reduction of inductor switching-node voltage stress, thereby achieving high-current operation and efficient power conversion. To further enhance current-sharing accuracy, a duty-cycle calibration circuit is introduced. Simulation results show that the proposed SCCH converter achieves a current-sharing mismatch within 0.9%, a peak efficiency of 91.2% under direct 48V-to-1V conversion, and a maximum output current of 30A with six phases, demonstrating its potential for 48V data-center power delivery.

This work proposes an avalanche-triggered dynistor (ATD) to simplify the driving of high-voltage pulsed-power switch stack. Local electric-field crowding in the ATD induces avalanche breakdown, and the generated carriers trigger regenerative thyristor turn-on, as clarified by TCAD simulations. When connected in series with a thyristor, the ATD enables the stack to be triggered by a conventional gate-drive signal applied only to the thyristor, avoiding stage-by-stage gate driving and energy-type dynistor triggering. With 1 to 4 ATDs connected in series with one thyristor, the stack operating voltage increases from 2.8 kV to 7.1 kV. Under the 7.1 kV condition with a pulse-loop resistance of approximately 30 mΩ, the stack achieves a peak current of 2.37 kA, a current rise rate of 15 kA/μs, and a pulse duration of approximately 370 ns.

A p-GaN gate high electron mobility transistor with the buffer avalanche triggered layer (BATL-HEMT) is experimentally demonstrated to exhibit repetitive avalanche-like behavior. One of the major limitations of conventional HEMTs is their limited avalanche capability, primarily due to the absence of an efficient removal path for the holes generated during avalanche breakdown. The local accumulation of these holes can indirectly induce severe thermal degradation, ultimately leading to potential device failure. However, in the proposed device, the unique P++P--N++ structure initiates an avalanche effect within the buffer layer, thereby activating the established hole energy dissipation pathway. Under multiple repeated breakdown testing, the device can instantaneously dissipate high current densities without observable thermal degradation. Additionally, temperature-dependent breakdown measurements show that the BATL-HEMT exhibits a positive temperature coefficient characteristic of avalanche breakdown.

To achieve higher pulse performance, conventional SiC drift-step-recovery diodes (C-DSRDs) require a larger peak reverse current. Accommodating this current typically necessitates an increased die area, which in turn degrades the pulse performance. To overcome these limitations, an anode-short DSRD (AS-DSRD) is proposed and investigated in this work. The proposed DSRD incorporates an additional N+ anode into the conventional P+ anode. During forward injection, a parasitic NPN transistor is formed, and the anode injection efficiency is reduced. In the proposed structure, the P-base region beneath the N+ anode is heavily doped to suppress the resulting local voltage drop that could trigger the parasitic NPN transistor. In the reverse-extraction phase, the parasitic NPN provides a low-resistance path, and the peak reverse current is not limited by the increase in dynamic resistance. Under nominal operating conditions, the proposed AS-DSRD exhibits a 1.35 & times; increase in dV/dt and a 1.11 & times; increase in Vpeak relative to the C-DSRD. Across a broad range of process and circuit parameters, it consistently maintains superior pulse performance, with the maximum improvement in dV/dt reaching 1.52 & times; and an average enhancement of approximately 1.30 & times;. These results demonstrate a more favorable trade-off between chip area and switching speed, underscoring the potential of the AS-DSRD for ultrafast high-voltage (HV) pulse applications.

In this letter, the variations of in-situ dynamic on-resistance (R-ON_dyn) of GaN enhancement transistors under heavy-ion radiations are presented for the first time. Different from the previous works analyzing R-ON_dyn only after radiations, the in-situ measurement is conducted by repetitive double pulse tests on GaN transistors with ohmic-contact gate (OG-HEMTs), Schottky-contact gate (SG-HEMTs) and cascode gate (CG-HEMTs). The OG-HEMTs exhibit a reduction of in-situ R-ON_dyn but an increase after radiations, while the R-ON dyn of SG-HMETs increases during the radiations and then recovers afterwards. Assisted by analysis of voltage transfer and gate leakage after radiations, continuous high level of holes injection through gate under heavy-ion radiations and related degradations in gate stack are the cause of an increase of over 40% post radiation, which is absent in SG-HEMTs. For CG-HEMTs, degradation and burnout of the cascode Si-MOSFET is the cause of R-ON dyn variation and device failures. This work can provide the second-thought and insights on the design of rad-hard GaN transistors by ohmic or Schottky hybrid gate structures.

This paper presents a novel three-phase sextuple step-down hybrid buck converter (TSHB) for direct 48V-to-PoL conversion. By reducing the voltage stress of inductor switching nodes to 1/6 VIN, the proposed TSHB achieves 6× duty-cycle extension and high efficiency with high figure-of-merit (FoM) devices. Additionally, the TSHB features self-balancing flying capacitor voltages and inherent phase current equalization, enabling reliable operation with a large output current. During heavy load transients, the unique transient state of the TSHB overcomes the 1/3 duty-cycle limit, resulting in over triple the total inductor current slew rate and markedly faster transient response. Experimental results validate the TSHB’s performance, demonstrating 86.5% peak efficiency at 48V-to-1V conversion with 333kHz switching per phase. Under a 50A load step within 500ns, TSHB exhibits only 178mV output voltage undershoot with 198μF output capacitance.

High-power pulse systems often require stacking multiple thyristors in series to withstand high-operating voltage, yet the optimal number of devices for maximizing pulse performance has remained unclear. This work develops a behavioral model for the pulse current in series-connected thyristors that links device-level conductivity modulation with circuit-level behavior. First, the drift region resistance of thyristors under high-current pulse conditions is characterized, accounting for drift region conductivity modulation in devices of different voltage ratings. This device behavior is then incorporated into an RLC discharge circuit model to derive analytical expressions for key pulse parameters, including the peak current (I-peak) and current rise rate (di/dt). The model reveals how increasing the number of series-connected thyristors can strengthen conductivity modulation and reduce the drift region resistance, thereby improving I (peak) and di/dt up to an optimal point. Simulation and experimental validations are presented for various operating voltages and configurations. The results show that the proposed model predicts the pulse current waveform and performance metrics for different series counts, matching measured waveforms closely. The model, for the first time, provides a quantitative design tool for high-voltage, high-current pulse power systems, and offers guidance on determining an optimal number of series-connected thyristors to achieve the best pulse performance.

To enhance tolerance of single event burnout (SEB) and single event gate rupture (SEGR), a 1200 V silicon carbide (SiC) lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS) with multilayer N-buffers and an embedded Schottky barrier structure (MBS-LDMOS) is proposed and characterized by Technology Computer Aided Design (TCAD) in this paper. At N-drift/N+ drain junction, the multilayer N-buffers spatially separate strong electric fields from large currents induced by irradiation. Within N-buffers, the power peak is reduced by more than an order of magnitude, while the overall distribution exhibits improved uniformity. Consequently, the maximum lattice temperature in MBS-LDMOS is limited by reduced heat power and an expanded energy dissipation area, decreasing from 2385 K in the conventional SiC LDMOS (C-LDMOS) at 300 V to 923 K in MBS-LDMOS at 600 V. For MBS-LDMOS, an SEB threshold voltage achieves 655 V under a linear energy transfer (LET) of 75 MeV·cm2/mg, corresponding to a 365 V improvement than that of C-LDMOS. Furthermore, when heavy ions strike SEGR sensitive position (right side of gate), the embedded Schottky contact and surrounding P-base provide additional paths to extract the heavy ion-induced holes accumulated beneath the gate oxide. Therefore, the proposed structure alleviates electric field crowding in the gate oxide, resulting in a maximum gate oxide electric field of 3.38 MV/cm for MBS-LDMOS with a LET of 75 MeV·cm2/mg, merely 26% of that in C-LDMOS under a $V_{\text{DS}}$ of 600 V.

Drift Step Recovery Diodes (DSRDs) are essential components in pulse generators, applicable to a broad spectrum of high-power and high-frequency applications. However, existing models predominantly emphasize device structural parameters while neglecting the critical influence of circuit parameters such as output current and pulse width. This study introduces a physical model for pulse generators that integrates drive circuit parameters and device structural parameters through rapid current interruption, thereby enhancing the accuracy of output pulse predictions and improving design efficiency. The proposed model calculates the current interruption phase by analyzing the turn-off oscillations of the MOSFET within the drive circuit and incorporates timedependent current dynamics to generate a temporal variation of the output voltage. Validation through extensive simulations and experimental measurements confirms the accuracy of the model in predicting key output pulse characteristics, including output voltage rise rate, and peak voltage, with relative deviations of less than 10% compared to simulation results and experimental results. Meanwhile, the model is capable of predicting the trend of the pre-pulse variation. Furthermore, the applicability of the proposed model has been thoroughly discussed, thereby providing a reliable tool for the optimization of DSRDs-based pulse generators. This work significantly contributes to the design of DSRDs-based pulse generators.

High-power pulsed generator systems typically require multiple DSRDs to be connected in series to withstand high operating voltages; however, how the number of series-connected DSRDs should be selected to maximize pulse performance has remained unclear. In this study, a behavioral model is developed to describe the pulse voltage in series-connected DSRDs, linking device-level conductivity modulation with circuit-level behavior. The model elucidates the mechanisms by which increasing the number of series-connected DSRDs enhances pulse performance, thereby improving Vpeak and dV/dt up to an optimal point. Simulation and experimental validations are carried out over a wide range of operating voltages and configurations. The results demonstrate that the proposed model can accurately predict performance metrics for different series numbers, showing excellent agreement with measured waveforms. For the first time, this model provides a quantitative design tool for high-voltage, high-current pulsed power systems and offers guidance for determining the optimal number of series-connected DSRDs to achieve superior pulse performance.

This study investigates the damage and performance degradation mechanisms in 4H-silicon carbide (SiC) MOSFETs induced by 25-MeV proton irradiation under varying drain-source voltages (V-ds) . The experimental results reveal three distinct voltage-dependent damage regimes: at high voltages, single-event effects dominate, leading to catastrophic single-event burnout (SEB); at medium voltages, a reduction in threshold voltage (V-th) , an increase in leakage current, and gate oxide damage are observed; at low voltages, the (V-th) increases and leakage current decreases, but the on-state resistance (R-on) exhibits a noticeable rise. Low-frequency noise (LFN) spectra confirm that the increase in V-th observed under low V(ds )conditions is primarily due to the reduction in interface trap density. Under medium V-ds, the observed decrease in (V-th) results not only from hole injection but also from an increase in interface trap density. These findings reconcile the electrical characterization results obtained under both low and medium V(ds )conditions. In addition, deep-level transient spectroscopy (DLTS) measurements confirm that the increase in bulk defects induced by proton irradiation is the main cause of the observed rise in R-on . The applied V-ds during irradiation accelerates the activation of passivated interface trap defects. This is because higher V(ds )leads to increased energy of interstitial atoms, resulting in the increased quantity of injected holes. The combined effect ultimately leads to a higher density of both interface and bulk defects.

In this work, a novel 4H-SiC n-type gate turn-off thyristor (GTO) with a PN stacked layer (PNSL) is proposed and investigated. Different from conventional SiC n-GTOs, the proposed PNSL SiC n-GTO features a stacked PN drift layer that reduces the effective charge density (Neff), accelerating depletion region expansion and shortening the voltage rise time (tv) during the turn-off process. Consequently, the proposed PNSL SiC n-GTO significantly reduces the turn-off loss (Eoff). Meanwhile, the PNSL optimizes the E-field distribution and improves immunity to dynamic avalanche, thereby enhancing the current handling capability. TCAD simulations demonstrate that compared to the conventional SiC n-GTO, the proposed PNSL SiC n-GTO achieves a 62% reduction in Eoff, a 35% increase in avalanche energy (EUIS), and a 17% increase in maximum non-destructive current, without compromising other device characteristics. Thus, the PNSL structure simultaneously reduces the Eoff and enhances the current handling capability of the SiC n-GTO.

In high-voltage pulsed-power systems, electromagnetic interference (EMI) can couple into the gate-drive path and induce false triggering of pulse switches, causing system-level malfunction and even damage. To mitigate this issue, this work demonstrates a dual-gate logic-controlled thyristor with an intrinsic AND-type turn-on criterion. Turn-on is permitted only when both gate channels are established. If either gate is inactive, the carrier-injection path remains incomplete and the device stays off-state, inherently suppressing false triggering. Experimental results show that single-gate driving keeps the device in the off-state, whereas dual-gate driving enables kA-class pulse discharge. Under interference conditions, the proposed device reduces the false-trigger count by more than 99%. These results indicate a substantially improved tolerance to EMI, making the proposed thyristor suitable for reliable pulsed -power switching in high-interference environments where conventional thyristors become unreliable.

Fast turn-off transitions of GaN HEMTs can excite commutation-loop LC resonance, causing severe VDS overshoot, high-frequency ringing, and EMI excitation. This paper proposes a monolithically integrable series-RC damping concept that embeds a plate-type field-plate capacitor and a resistive element in the field-plate region to form a compact, low-inductance damping loop without adding system volume. The capacitor is geometry-defined and exhibits weaker voltage dependence than junction-based capacitances, maintaining effective absorption under high blocking voltage. A circuit-informed co-design flow is developed: the dominant ringing is characterized from Lloop and Coss , the target Csnub /Rsnub are selected with the local snubber-loop inductance considered, and then mapped to realizable on-chip geometries. Sentaurus TCAD and LTspice simulations clarify that the proposed structure preserves DC characteristics and that damping effectiveness is strongly limited by snubber-loop parasitic inductance. To validate the mechanism without an integrated prototype, board-level double-pulse tests (DPT) at 400 V employ a discrete series-RC branch as an emulation platform under identical power-loop and gate-drive conditions. The RC-assisted configuration achieves up to 19.8% reduction in VDS overshoot and up to 40.5% reduction in ringing settling time, and reduces high-frequency spectral components by 8 dB at 205 MHz.

A monolithic GaN bidirectional load switch (BLS) with a fast turn-on control (FTC) technique and inrush current protection is proposed in this paper. By utilizing an integrated sense-BLS, the FTC driver accurately tracks the Miller platform to achieve rapid fully turn-on the BLS without overcurrent risk. Moreover, the design introduces a 100% duty-cycle bootstrap supply adopting a pre-charged pumping capacitor, enabling the maximum 100% duty-cycle operation. The proposed GaN BLS is simulated in Cadence Virtuoso where its inrush current protection capability and fast switching performance are verified.

In this work, the n-type resistive field plate (RFP) is proposed and experimental demonstrated on p-GaN high electron mobility transistors (RFP-HEMTs) with enhanced on-state and off-state performance simultaneously. The RFP-HEMT features a high-resistivity titanium oxynitride (TiNxOy) resistive passivation layer, which extends from the source toward the drain. Due to the surface potential (V-surf) modulation effect and the two-dimensional electron gas (2-DEG) enhancement effect, the proposed RFP-HEMTs not only realized a higher breakdown voltage (BV) in the off-state but also reduced the on-state resistance (R-ON) in the on-state. Additionally, dynamic R-ON degradation and threshold voltage (VTH) instability are effectively suppressed. Compared with the conventional insulator passivated devices, the BV of optimized RFP-HEMTs reaches 1800 V, and the figures-of-merits (FOMs) of RFP-HEMTs with the gate-to-drain distance of 20 mu m improved by 428.78% Moreover, an optimized dynamic/static R-ON ratio of 1.15 is obtained, along with a suppressed shift of VTH within 20 mV. The results demonstrate that the n-type RFP technology can improve the static and dynamic performance in p-GaN gate HEMTs.

The Insulated Gate Bipolar Transistor (IGBT), as a bipolar device, continuously faces the challenge of balancing its conduction and turn-off performance throughout structural evolution. Double-gate structures offer a solution to this problem. The planar gate structure offers inherent advantages in process simplicity, lower fabrication cost, and superior gate oxide reliability. Motivated by these benefits, this work proposes a 1700 V planar double-gate IGBT with distinct driving strategies for two types gate. This structure reduces the stored carrier concentration near the emitter during turn-off, thereby accelerating turn-off. Consequently, it achieves lower turn-off losses than a single-gate IGBT. This work first systematically investigated and optimized key parameters such as gate ratio and turn-off delay time by Sentaurus TCAD to evaluate their impact on device performance. Ultimately, the fabricated DG-IGBT sample exhibits a blocking voltage of 1700 V and maintains onstate voltage equivalent to conventional IGBTs. Turn-off tests measured a 32 % reduction in turn-off loss compared to single-gate.

Repetitive Marx generator based on GaN HEMTs is proposed and experimentally verified. The self-triggering GaN Marx generator prototypes are realized and only one gate driver ICs is required. With a DC input ranging from 100 to 500 V, the proposed GaN Marx generators consistently produce output voltage pulses at repetition frequencies between 10 and 100 kHz, achieving a voltage conversion efficiency (VCE)—defined as the ratio of output voltage to the product of the number of stages and input voltage—of 100%. The 5-stage Marx generator utilizing GaN HEMTs delivers pulses with a peak voltage of 2.5 kV, a rise time of 6.4 ns, and a repetition rate of 100 kHz. This overall performance surpasses that of previously reported Marx generators using Si avalanche transistors, SiC MOSFETs, and GaN HEMTs. Therefore, the proposed GaN HEMT-based Marx generator presents a highly promising solution for applications requiring highly repetitive pulsed power supplies.