We investigate AlN/GaN MISHEMTs fabricated on a 200 mm Si substrate with an in-situ SiN as the gate insulator and access region passivation layer. The impact of SiN thickness scaling on the large-signal performance is analysed using pulsed IV characterisation combined with first-order load-line-based formulae to quantify the degradation in Pout and PAE stemming from increased trapping-induced current collapse associated with thinned-down SiN thicknesses. At 28 GHz, large-signal characterisation, including tuning up to the third harmonic, reveals a competitive linear gain of 15 dB and PAE of 62.5% at 6 V, making these devices suitable for user equipment intended for FR2/FR3 operation.

Gate current is known to limit device performance, yet a detailed analysis of its impact on RF power performance has not been extensively documented. This article examines the influence of gate current on RF power performance. A small-signal equivalent-circuit analysis shows that gate current degrades the device's RF power performance, with higher gate currents causing greater degradation. In addition, the effect of gate current varies with frequency due to the frequency-dependent impedance of C-gs and C-gd, resulting in more significant degradation at lower frequencies because of the parallel connection of gate conduction with these capacitors. These findings are validated under large-signal conditions using an experimentally verified device model for InAlN/GaN high-electron-mobility transistors (HEMTs).

This work studies two calibration methods for S-parameter measurements by a real-time oscilloscope (RTO). Vector Network Analyser (VNA) measurements of an active and passive device, calibrated with an eight-term Short Open Load Reciprocal (SOLR) algorithm, are compared to RTO measurements with SOLR calibration applied via two methods from literature. The methods differ in the order of S-parameter calculation from the RTO measured travelling voltage waves and in their error models. Method one, the traditional method (TM), converts the raw waves to S-parameters before calibration and utilises the twelve-term model. Method two, relative wave calibration (RWC), corrects the raw waves via the eight-term model and calculates S-parameters at the end. The TM provided the closest match to VNA data with a maximum 2.31% error in transmission and so is recommended for RTO vector calibration.

We demonstrate GaN-on-Si HEMTs capable of meeting mm-wave requirements. We compare the large-signal performance for thin barrier AlGaN/GaN and InAlN/GaN-based HEMTs with gate lengths downscaled to 70nm at 28GHz using passive load-pull characterisation. The 8x25µm InAlN/GaN devices with a 100nm gate length achieve a P SAT of 2.8W/mm and a corresponding PAE of 50% at 28GHz at 10V operation in class AB, thereby showing their suitability for power amplifiers in battery-powered user equipment at mm-wave. Finger width reduction for these 8-finger InAlN/GaN devices boosts the normalised P SAT up to 3.9W/mm at a 150nm gate length.

We report high performance AlN/GaN MISHEMTs grown using MOCVD on 200 mm Si substrates with in-situ silicon nitride (Si 3 N 4 ) as the common gate insulator and access region passivation layer. The RF small and large-signal performance trade-offs of AIN and Si 3 N 4 thickness scaling are systematically examined. Ultra-thin barrier and dielectric stacks (AIN < 2.5 nm, Si 3 N 4 ≤ 2 nm) lead to excellent small-signal performance with peak f max : ~190 GHz at 110 nm gate lengths but trapping induced current collapse is worsened, degrading the RF large-signal performance. For thicker stacks (AIN ≥ 2.5 nm and Si 3 N 4 ≥ 3 nm), current collapse is lower and large-signal performance improves significantly while still maintaining. f max >150 GHz with good linearity. Record large-signal performance (@ 28 GHz) at 200 μm gate width is demonstrated with a P SAT : 2.2 W/mm (26.8 dBm) and PAE : 55.5% at V d : 10 V and a P SAT : 2.8 W/mm (27.5 dBm) and PAE : 54.8% at V d : 20 V.

Thin channel GaN HEMTs intended for mm-wave operation suffer from increased on-resistance (R ON ) dispersion, limiting their large-signal performance. This work establishes a composite AlGaN/cGaN back barrier (BB) as a plausible solution to reduce the trapping in the BB while improving the 2DEG confinement. Large-signal characterisation at 28GHz, using source- and load-pull, indicates a significant improvement in P SAT and PAE for devices with an AlGaN/cGaN BB, compared to those with a cGaN BB only, due to their lower current collapse.

Short-channel Gallium Nitride (GaN) high-electron-mobility transistors (HEMTs) often utilize T-shape gates due to their large gate-line cross-sectional area and subsequent f(MAX) increase. In this paper, we report the linearity trade-offs associated with varying the T-gate geometries of AlGaN/GaN HEMTs on Si, specifically the gate extensions which serve as field plates and their impact on the large-signal performance. Small-signal characterization and modeling, in addition to TCAD, provide initial guidelines for the optimal dimensions for the gate field plates using the ratio of f(T) and the product of the gate resistance and the gate-to-drain capacitance. We utilize various characterization methods, including 6 GHz non-linear vector network analyzer characterization in addition to load-pull, to quantify the amplitude and phase distortion and their subsequent impact on the large-signal metrics of the devices under differing matching conditions and bias points. We deduce that the influence of the gate field plates on the amplitude and phase distortion is non-negligible, particularly under matched conditions.

We examine the influence of scaling the GaN channel thickness from 100nm to 35nm on the RF performance for GaN HEMTs on Si with a cGaN back-barrier with gate lengths ranging from 70nm to 190nm. Thinner GaN channels notably improve the short channel effects. However, there is a degradation in the on-state performance associated with an increase in dispersion. These trade-offs translate to a ~33%, ~20% decline in $f_{\mathrm{T}}, f_{\text{MAX}}$ respectively, for 70nm devices. While the large-signal metrics, PSAT and PAE, at 6GHz drop by ~46% and ~18%, respectively. We also consider the lateral downscaling of the gate-to-drain and gate-to-source spacings, which proves beneficial in boosting PSAT, up to 3.4W/mm, by increasing the extrinsic transconductance by ~20%.

Abstract : GaN-on-Si HEMTs are emerging as a viable candidate for front-end-of-module (FEM) implementation in 5G and beyond user equipment and small-cell applications [1][2]. This is because GaN HEMTs based power amplifiers and switches have high power handling capability as well as excellent switch figure-of-merit (Ron × Coff). The cost-effective integration of GaN HEMTs on silicon substrates not only benefit from standard CMOS back-end-of-the-line processing but also wafer-level integration with Si-CMOS [1][3], enabling complex functionality and better performance than the standalone counterparts. An example can be a hybrid beamformer where GaN HEMTs can enable much smaller antenna array and therefore a smaller system form factor. For 5G wireless applications, standalone or co-integrated GaN HEMT based FEMs can lead to a more energy efficient and compact system as compared to standalone Si-CMOS technologies. However, for both amplifiers and switches, GaN-on-Si HEMTs present thermal management and substrate loss related issues. In this work, we study and model the impact of GaN HEMT integration on Si substrate on RF substrate losses and non-linearities. The growth of III-N buffer is the most significant factor in determining RF losses and harmonic distortion contribution from the substrate. High temperature annealing and ion implantation steps encountered during HEMT processing can also degrade the substrate performance. In addition, we demonstrate a direct co-relation between substrate losses and harmonic distortion analogous to silicon-on-insulator technologies (Figure 1). However, the bias dependence of RF losses and harmonics show a strong time dependence (memory effects) which is more complex to model [11]. We discuss the approaches to understand and model these effects. References: [1] H. W. Then et al, IEEE IEDM Tech. Dig., 2021, pp. 230-234. [2] B. Parvais et al, IEEE IEDM Tech. Dig., 2020, pp. 155-158. [3] W. E. Hoke et al, J. Vac. Sci. Technol. B 30, 02B101 (2012). [4] Drillet F et al, IJMWT 13, 517–522, 2021. [5] L. Cao et al, CSMANTECH conference Tech. Dig., 2020. [6] Roda Neve et al, IEEE TED, Vol. 59, NO. 4, pp. 924-932, 2012. [7] S. Yadav et al., in IEEE IEDM Tech. Dig., 2020, pp. 159-162. [8] Rack et al, ECS Trans., 92 (4), pp. 79-94, 2019. [9] Zhu et al, IEEE Microw. Wireless Compon. Lett., vol. 28, no. 8, pp. 377–379, 2018. [10] Raskin et al, IEEE SiRFIC, 2015. [11] P. Cardinael et al, IEEE ESSDERC 2021, pp. 303-306. Figure 1

This work investigates scaling of the GaN channel thickness on top of a carbon-doped GaN buffer (cGaN) grown on 200mm Si substrates. Device performance tradeoffs are analyzed in terms of DC, RF, reliability and thermal behavior. A thinner channel improves DIBL, $I_{off},V_{th}$ roll-off and degrades $f_{T},f_{\max}$ , PAE, Pout, charge trapping and thermal conductance characteristics. Transconductance was observed to increase under high saturation drain bias for thin and short channels indicating the lateral device scaling potential of cGaN based HEMTs.

In this paper, we will discuss the progress that has been made in upscaling GaN and InP to a Si platform as well as making them CMOS and 3D compatible to enable the heterogeneous systems that will be needed for 5G mm-wave and 6G sub-THz frequencies for high-capacity wireless communication.

Trapping in an impurity (e.g. Fe, C) doped back barrier (BB) causes pronounced on-resistance (R on ) dispersion of GaN HEMTs. We demonstrate that the BB trapping is alleviated by increasing 2DEG density N sh in the GaN channel (~50% increased N sh results in ~30% less $\Delta \mathrm{R} _{on})$ and inserting an additional intrinsic AlGaN BB (100 nm AlGaN with ~50% less $\Delta \mathrm{R} _{on})$. We propose a novel flat-AlGaN-BB-energy-band designing criterion for the AlGaN/C-GaN BB combination.

A review of the modelling requirements to establish a Design-Technology Co-Optimization loop for mmWave Front-End Modules is presented. The example of GaN/Si technology is detailed, and recent modeling developments are explained

GaN-on-Si HEMTs are one of the leading technology options for 5G and beyond frond-end-modules. Substrate RF losses and harmonic distortion degrade performance of both active as well as passive devices for power amplifier and switch applications. In this paper, we report on the substrate RF loss and linearity performance of GaN-on-Si technology. It is shown that coplanar waveguides on GaN-on-high resistivity (3–6 kΩ·cm) CZ-Si wafers can achieve 2nd harmonic levels ~ −85 dBm (on a 2 mm long CPW line at Pout ~15 dBm) with effective resistivity ρeff ~1 kΩ·cm. The impact of HEMT fabrication process and epitaxy on RF losses and distortion is studied and relationship between losses and distortion is discussed.

We investigate the effect of varying the gate-to-drain spacing and the gate field-plate on the device linearity of GaN HEMTs on Si for 0.11μm, 0.15μm, and 0.19μm gate lengths. The gain compression, phase distortion, and harmonic distortion metrics are measured using a nonlinear characterisation setup calibrated at 6GHz up to the third harmonic. The acquired nonlinearity metrics are correlated with the extrinsic device parasitics extracted from S-parameter measurements. We observe that excessive gate field-plate length scaling down to 0.05μm lowers the total phase distortion at the expense of gain linearity and harmonic distortion in Class AB while minimising the gate-to-drain spacing alleviates the harmonic distortion only for devices of 0.19μm gate length. Further evaluation, under matched conditions, using a passive load-pull measurement setup points to a decline in the peak achievable PAE and PSAT at gate field-plates smaller than 0.12μm.

We report on the development of mm-wave GaN-on-Si AlGaN HEMTs integrated with a 3 level Cu damascene BEOL flow on 200mm Si <111> wafers. Optimizations of the gate metal stack, contact resistance and gate length scaling to 110nm result in devices with a peak gm of 430 mS/mm and an fMAX of 135 GHz. While wafer warp was found to increase slightly through the processing of 3 levels of 1µm thick Cu metal, no significant deterioration was observed between devices measured at Metal 1 and Metal 3.

The world is more than ever relying on connectivity in our daily life as well as our professional life. With 5G being rolled out, the industry is looking already at the next generation of mobile communication to bring even higher speeds and more connections than previous generations. But with 5G we are at an inflection point where it is not only about higher data rates and more connections, but about connecting different kind of devices and the new ways humans and machines interact with each other. The higher frequencies, low latency and reliability requirements will put a lot of strain on the technologies to enable this. While CMOS is the preferred vehicle, to fulfill these demands compound semiconductors like GaN and InP might be the better options for particular functions of the radio architecture. This paper will address the progress toward upscaling these materials to a Si platform and to make them CMOS and 3D compatible to enable the final heterogeneous systems that will be needed for 5G and beyond.

To enable CMOS-compatible GaN HEMTs for the next generation of communication systems (5G and beyond), a low gate resistance is of great importance since it directly affects the RF power gain and f MAX of the transistor. In this article, the impact of various gate-metal stacks on the gate resistance and RF performance of the devices is studied. The optimized Ti-free gate-metal process leads to f MAX enhancement up to ~50% for devices scaled down to 0.32-μm gate lengths. The gate resistance for the T-shaped gate is modeled from the S-parameters and validated on various gate field plate geometries. The tradeoff between the gate resistance and the parasitic capacitance in GaN HEMTs is highlighted in this case.

The growing interest for 5G radios pushes technology development towards low-cost and high-performance solutions for operating at microwave and mm-wave. Downscaling CMOS technology has allowed the integration of high-speed transceivers on silicon chips, but high-power amplifiers rely on III-V technologies to deliver the power and efficiency levels required by modern radios. In this work, we motivate the interest of non-Si technologies to meet 5G requirements, and we explore two routes to enable the fabrication of compound semiconductor devices on a large-scale manufacturable Si platform [1,2]. We provide insight on the potential of these new technologies for the design of advanced front-end modules, including modelling and reliability challenges. In the first route (Figure 1(a)), we report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools, and discuss the performance trade-offs, limitations and solutions. State-of-the-art contact resistance of 0.14 Ω.mm is demonstrated for a non-Au, low thermal budget (<600 oC) contact scheme, as well as a high vertical breakdown voltage (VBD) of >300 V. We show that MISHEMTs, which feature the highest field effect mobility (μFE), >2000 cm2/V.s, and the best 1/f noise performance, have the potential to outperform the other device types in terms of device scalability for high frequency operation. The GaN-on-Si substrate optimization for low RF losses and nonlinear distortion is further discussed. The second route (Figure 1(b)) includes the formation of HBT on Si wafer by selective epitaxy. We demonstrate GaAs/InGaP HBTs grown on a 300 mm Si substrate. A DC current gain of ~112 and breakdown voltage, BVCBO, of 10 V is achieved. The emitter-base and base-collector diodes show an ideality factor of ~1.2 and ~1.4, respectively. This demonstration shows the potential for enabling a hybrid III-V CMOS/ technology for 5G and mm-wave applications, not limited to GaAs but which can also be extended to InGaAs on a 300 mm Si substrate. Figure 1

In this work, we will address the opportunities of a hybrid III-V/CMOS technology for next generation wireless communication, beyond 5G, moving to operating frequencies above 100GHz. Challenges related to III-V upscaling and CMOS co-integration using 3D technologies will be discussed.