We report a comprehensive analysis of the leakage current mechanism in ion implantation isolation (I/I/I) regions of GaN high electron mobility transistors. We applied a three-step high-energy low-dose N I/I/I to AlGaN/AlN/GaN heterostructures. High-quality isolation is achieved with isolation sheet resistances Rsh in the range of 1013–1015 Ω/sq. The analysis of isolated heterostructures with varied AlGaN or AlN thicknesses indicates common electron leakage paths at the surface of GaN. The electrostatics of the leakage path is determined by an interplay between the high densities of defects created by I/I/I, the net sheet polarization charges between III-nitrides, and the AlGaN surface states. We find that the activation energy of Rsh positively correlates with the energy level of the leakage path. The energy band diagram of the isolation region is constructed by correlating the activation energies of Rsh with the heteerostructure electrostatics. Moreover, our study makes a novel method to estimate the net active defect density caused by I/I/I: net active defect densities of ∼2 × 1019 and ∼2 × 1018 cm−3 are extracted in the GaN and AlGaN layers, respectively.

This work investigates scaling of the GaN channel thickness on top of a carbon-doped GaN buffer (cGaN) grown on 200mm Si substrates. Device performance tradeoffs are analyzed in terms of DC, RF, reliability and thermal behavior. A thinner channel improves DIBL, $I_{off},V_{th}$ roll-off and degrades $f_{T},f_{\max}$ , PAE, Pout, charge trapping and thermal conductance characteristics. Transconductance was observed to increase under high saturation drain bias for thin and short channels indicating the lateral device scaling potential of cGaN based HEMTs.

This work shows that the complex dynamic-RON characteristics observed for scaled GaN HEMT devices results from the similar capture/emission activation energies of the defects present in different epitaxial layers. This work also (i) presents an optimized experimental scheme for a detailed analysis of the different charge-trapping mechanisms in GaN-on-Si HEMTs, (ii) describes the charge-trapping kinetics over a wide range of temperatures using capture/emission time (CET) maps, and (iii) models the defect energy distribution in the AlGaN barrier by analytically deriving the 2D potential profile in the access region and combining it with the results from CET maps.

Temperature dependence of charge capture and emission in HfO2 and ferroelectric doped HfO2 are examined over a wide temperature range. Sizeable threshold voltage (V-th) instabilities are observed under cryogenic conditions, contrary to expectation of Arrhenius-based defect freeze-out. The observed data is modelled with ultra-fast defect levels, located close to the silicon channel. The impact of these traps at room temperature on ferroelectric devices is significant: capture and emission times lie in the range applied for ferroelectric device operation, and can explain the read-after-write delay incorporated in Si-based ferro (FE-)FET operation.

We report on our extensive experimental and simulation study to understand ESD failure mechanisms in RF GaN-on-Si (MIS)HEMTs. As opposed to ESD clamp transistors in LV CMOS technologies, a mis-correlation between standard-defined HBM ESD robustness and commonly used TLP failure current was observed in GaN (MIS)HEMTs. Using transient HBM IV characteristics, a novel discharge model is proposed to explain the transient discharge mechanism. The TCAD and SPICE simulations confirmed that the observed mis-correlation between TLP and HBM is attributed to 2DEG channel resistance modulation in response to HBM ESD transient voltage waveforms.

A review of the modelling requirements to establish a Design-Technology Co-Optimization loop for mmWave Front-End Modules is presented. The example of GaN/Si technology is detailed, and recent modeling developments are explained

Scaling from FinFETs to horizontal and vertical single or stacked nanowires and nanosheets directly impacts the low frequency noise performance. The processing choice (e.g. gate stack, junction architecture, metal stack) also plays an important role. The noise power spectral density (PSD) of advanced Si, Ge and III-V devices is studied and compared with each other.

The GaN-on-Si technology for the upcoming RF/6G/mm-Wave applications requires a robust buffer design for enhanced device performance and improved reliability. The defect states present in the various layers of the buffer stack can have a detrimental impact on both the DC and the AC performance of the device, as they can interact with the 2DEG channel carriers and/or contribute to buffer leakage mechanisms. An important reliability concern is the dynamic-RON, arising from the interaction of the 2DEG channel with the defects in the buffer stack and/or the defects in the barrier layer or barrier/cap interface. In this work, an improved and more robust current transient spectroscopy technique is used to extract the time constant spectra and the activation energies of various buffer defects. A thinner GaN channel layer is shown to increase the dynamic-RON, while a specific buffer stack configuration is shown to have a considerable impact the dynamic-RON.

We investigate the effect of varying the gate-to-drain spacing and the gate field-plate on the device linearity of GaN HEMTs on Si for 0.11μm, 0.15μm, and 0.19μm gate lengths. The gain compression, phase distortion, and harmonic distortion metrics are measured using a nonlinear characterisation setup calibrated at 6GHz up to the third harmonic. The acquired nonlinearity metrics are correlated with the extrinsic device parasitics extracted from S-parameter measurements. We observe that excessive gate field-plate length scaling down to 0.05μm lowers the total phase distortion at the expense of gain linearity and harmonic distortion in Class AB while minimising the gate-to-drain spacing alleviates the harmonic distortion only for devices of 0.19μm gate length. Further evaluation, under matched conditions, using a passive load-pull measurement setup points to a decline in the peak achievable PAE and PSAT at gate field-plates smaller than 0.12μm.

In this paper, Gallium Nitride (GaN) Metal-Insulator-Semiconductor (MIS)-HEMTs are compared with conventional Schottky Metal-Semiconductor HEMTs in terms of DC and ESD performance. Measurement results indicate TLP failures are highly related to 2DEG channel driving capability. The impacts of different gate interfaces in the GaN (MIS)-HEMTs on failure mechanisms are the key factor of final ESD robustness.

In this article, GaN/AlGaN metal-oxide-semiconductor high-electron-mobility field-effect transistors (MOSHEMTs) fabricated on high-resistivity Si (111) substrates have been evaluated using low-frequency (LF) noise measurement. The noise power spectral density (PSD) of devices with different lengths and channel orientations has been characterized in linear operation. No noticeable differences in the electrical and noise PSD characteristics have been observed between the GaN [1 (1) over bar 00] and [11 (2) over bar0] channel orientations. While most devices are dominated by 1/ f noise, originating from number fluctuations, for long devices (L >= 1.1 mu m), additional generation-recombination (GR) noise has been observed, originating from traps in the GaN layer.

The impact of the short gate length on the drain current and low frequency (LF) noise in GaN/AlGaN metal-oxide-semiconductor high-electron-mobility field-effect-transistors has been studied. In some short devices, a parasitic subthreshold current is observed. In this article, the origin of parasitic subthreshold currents were explored using LF noise and trapping transient measurements. The LF noise power spectral density (PSD) of the devices without parasitic drain current decreased monotonically with the decrease of the drain current, while the PSD of the device with the parasitic drain current strongly increased for lower drain current. The 1/ f 1.5 noise corresponding with the parasitic leakage can be explained by the level broadening of generation-recombination centers in the GaN channel. This is confirmed by the trapping transient measurements, revealing a temperature-independent time constant, associated with the leakage path in short channel transistors, exhibiting the subthreshold humps.

We report on the development of mm-wave GaN-on-Si AlGaN HEMTs integrated with a 3 level Cu damascene BEOL flow on 200mm Si <111> wafers. Optimizations of the gate metal stack, contact resistance and gate length scaling to 110nm result in devices with a peak gm of 430 mS/mm and an fMAX of 135 GHz. While wafer warp was found to increase slightly through the processing of 3 levels of 1µm thick Cu metal, no significant deterioration was observed between devices measured at Metal 1 and Metal 3.

We evaluate the total-ionizing-dose (TID) responses of InGaAs nMOS fin field-effect transistors (FinFETs) with a modified gate-stack irradiated with 10-keV X-rays under different gate biases. This modified InGaAs nMOS FinFET process shows decreased subthreshold leakage current and increased hysteresis in as-processed devices, and reduced hole trapping in irradiated devices, than first-generation d...

GaN-channel based transistors are ideally suited for RF/5G applications and also provide the promise of monolithic integration on a conventional Si-platform. Due to the wide scope of high electron mobility GaN transistor architectures, their reliability assessment is essential to ensure their successful deployment in low-power applications such as mobile computing devices, as well as high-power applications such as autonomous vehicles and base stations. We identify the most important DCreliability metrics necessary for fair benchmarking of future GaNon-Si RF transistors. A detailed analysis of the shortlisted DCreliability parameters for three device types, namely MOSFETs, MOSHEMTs/MISHEMTs and HEMTs is presented. MOSHEMT/MISHEMT is identified as the most robust device architecture, due to the presence of a barrier layer alleviating the impact of certain degradation mechanisms. Defect distributions in the gate-stack of MOS devices are extracted using defect band modelling technique. MOSHEMT devices are shown to undergo negative and positive Bias Temperature Instability (BTI) under specific ranges of positive gate-overdrive, thereby demonstrating the importance of correctly estimating the oxide field for MOSHEMT devices. Degradation map methodology is partially developed to distinguish the different gate-oxide degradation mechanisms and model the device lifetime pertaining to each of the mechanisms.

The world is more than ever relying on connectivity in our daily life as well as our professional life. With 5G being rolled out, the industry is looking already at the next generation of mobile communication to bring even higher speeds and more connections than previous generations. But with 5G we are at an inflection point where it is not only about higher data rates and more connections, but about connecting different kind of devices and the new ways humans and machines interact with each other. The higher frequencies, low latency and reliability requirements will put a lot of strain on the technologies to enable this. While CMOS is the preferred vehicle, to fulfill these demands compound semiconductors like GaN and InP might be the better options for particular functions of the radio architecture. This paper will address the progress toward upscaling these materials to a Si platform and to make them CMOS and 3D compatible to enable the final heterogeneous systems that will be needed for 5G and beyond.

A high gate-stack breakdown voltage is desired to enable the GaN-on-Si (MIS)HEMT device technology for upcoming RF/5G and mm-Wave applications. In this work, we show that the gate field-plate length (LGFP) has a considerable impact on the gate-stack TDDB lifetime for different gate-stack processing conditions and varying AlGaN barrier thickness. The TDDB lifetime is observed to increase with LGFP for devices suffering from high pre-stress gate-leakage, while it is observed to reduce with LGFP for devices with low gate-leakage and high RON dispersion. In devices with thinner AlGaN barrier, the higher RON dispersion results in further reduction of the TDDB lifetime. Additionally, the impact of LGFP on the TDDB lifetime is observed to reduce with thinner AlGaN barrier under similar processing conditions These results indicate a strong correlation between the gate-leakage and the barrier/cap interface properties, and their combined effect on the TDDB lifetime.

This paper describes the application of Deep Level Transient Spectroscopy and Generation-Recombination Noise Spectroscopy to the study of trap levels in III-V and III-N materials and devices.

The growing interest for 5G radios pushes technology development towards low-cost and high-performance solutions for operating at microwave and mm-wave. Downscaling CMOS technology has allowed the integration of high-speed transceivers on silicon chips, but high-power amplifiers rely on III-V technologies to deliver the power and efficiency levels required by modern radios. In this work, we motivate the interest of non-Si technologies to meet 5G requirements, and we explore two routes to enable the fabrication of compound semiconductor devices on a large-scale manufacturable Si platform [1,2]. We provide insight on the potential of these new technologies for the design of advanced front-end modules, including modelling and reliability challenges. In the first route (Figure 1(a)), we report on Al(Ga,In)N HEMTs, MISHEMTs and MOSFETs integrated on 200 mm Si wafers using Au-free processing in standard Si CMOS tools, and discuss the performance trade-offs, limitations and solutions. State-of-the-art contact resistance of 0.14 Ω.mm is demonstrated for a non-Au, low thermal budget (<600 oC) contact scheme, as well as a high vertical breakdown voltage (VBD) of >300 V. We show that MISHEMTs, which feature the highest field effect mobility (μFE), >2000 cm2/V.s, and the best 1/f noise performance, have the potential to outperform the other device types in terms of device scalability for high frequency operation. The GaN-on-Si substrate optimization for low RF losses and nonlinear distortion is further discussed. The second route (Figure 1(b)) includes the formation of HBT on Si wafer by selective epitaxy. We demonstrate GaAs/InGaP HBTs grown on a 300 mm Si substrate. A DC current gain of ~112 and breakdown voltage, BVCBO, of 10 V is achieved. The emitter-base and base-collector diodes show an ideality factor of ~1.2 and ~1.4, respectively. This demonstration shows the potential for enabling a hybrid III-V CMOS/ technology for 5G and mm-wave applications, not limited to GaAs but which can also be extended to InGaAs on a 300 mm Si substrate. Figure 1