This paper is a case study of diagnostic techniques used to debug a particularly difficult fail in a multi-port register file memory that appeared to increase its minimum functional voltage (VMIN) over time. Some of the debug techniques used involved Array Built-In-Self Test (ABIST) before and after chips in burn in, CPA (Critical Parameters Analysis), PEM (Photon Emission Microscopy), PICA (Picosecond Image Circuit Analysis) and PFA (Physical Failure Analysis).

Maze running games represent a popular genre of video games and the design of playable mazes provides an interesting research challenge in procedural content generation for computational intelligence research in games. In this paper, we attack the problem of creating playable mazes by using genetic algorithms to evolve cellular automata rules that lead to playable mazes. More specifically, a fixed number of evolved-rule applications generates maze like patterns on a cellular automata grid and a region merging algorithm then generates the final, playable maze. Since maze path lengths correlate with maze playability, the genetic algorithm searches for cellular automata rules that lead to longer path lengths. Results from two types of cellular automata and three different fitness functions of path length show that our approach results in a variety of interesting, playable mazes with longer path lengths and complex paths.

In this paper we propose an interactive genetic algorithm to evolve maze levels for computer games. We represent a maze with a cellular automaton and the genetic algorithm evolves the cellular automata rules applied to a starting maze level state. Users then rate the fitness of a subset of the generated population using an image of the top-down view of the maze. After ten generations, users then play through the best evolved maze within a maze runner type game using a first person perspective. User ratings show that our IGA was able to evolve highly rated mazes.

Reliability is a key concern for VLSI circuits especially so for latches and memories due to their small feature sizes. Particularly, for SRAM cell designs Bias Temperature Instability effects have significant implications on functionality and performance. Here we propose through simulation and modeling an efficient statistical methodology to evaluate and minimize the aging of memory chips. Redundancy has been typically used to resolve failing parts at beginning-of-life. In this approach, we propose to use redundancy to repair critical parts that are most susceptible to aging, thereby optimizing end-of-life yield. Our methodology enables what would have been a very expensive and exhaustive hardware testing approach by identifying optimal repair corners via fast statistical simulations. The methodology takes into consideration reliability effects in the presence of random process variation. This in turn identifies critical repair parts for optimal yield and helps minimize the ever increasing field failure problem.

We propose a new and efficient statistical-simulation-based test methodology for optimally selecting repair elements at beginning-of-life (BOL) to improve the end-of-life (EOL) functionality of memory designs. This is achieved by identifying the best BOL test/repair corner that maximizes EOL yield, thereby exploiting redundancy to optimize EOL operability with minimal BOL yield loss. The statistical approach makes it possible to identify such corners with tremendous savings in terms of test time and hardware. To estimate yields and search for the best repair corner the approach relies on fast conditional importance sampling statistical simulations. The methodology is versatile and can handle complex aging effects with asymmetrical distributions. Results are demonstrated on state-of-the-art dual-supply memory designs subject to statistical negative bias temperature instability (NBTI) effects, and hardware results are shown to match predicted model trends.

The 65 nm cell broadband enginetrade (cell BE) is a multi-core SoC, implemented in a high performance SOI technology featuring a separate dual power supply for SRAM arrays to improve stability and performance using an elevated voltage. A new method is shown to analyze the SRAM cell under application conditions which was used to tune the cell for stability, write-ability and performance. An improve...

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well CMOS technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

The 65nm CELL Broadband Enginetrade design features a dual power supply, which enhances SRAM stability and performance using an elevated array-specific power supply, while reducing the logic power consumption. Hardware measurements demonstrate low-voltage operation and reduced scatter of the minimum operating voltage. The chip operates at 6GHz at 1.3V and is fabricated in a 65nm CMOS SOI technology.