This brief theoretically investigates the impact of reducing idle time-the dead time between consecutive chirps-on the performance of frequency-modulated continuous-wave (FMCW) radar systems. The results show that reducing idle time while maintaining the chirp bandwidth helps lower the chirp slope, offering several key advantages. First, it alleviates the effects of reciprocal mixing caused by system phase noise (PN), thereby improving the signal-to-noise ratio in multi-target scenarios. Second, it enhances the range correlation effect, further mitigating phase noise and improving target detection capabilities. Third, this adjustment relaxes the requirements for the analog-to-digital converter. Finally, it improves chirp linearity and range resolution by enabling the use of an FMCW signal with a lower chirp slope. These findings are supported by theoretical analysis and validated through simulation results.

This brief proposes a structure to enhance the bandwidth of type-I sub-sampling phase-locked loops (SSPLL) without compromising the loop stability. A voltage-controlled delay line (VCDL) is employed at the output of the voltage-controlled oscillator (VCO) to readjust the phase of the VCO. The delay of this VCDL is controlled based on the instantaneous phase of the VCO, extracted at the output of the phase detector. Using theoretical analysis and simulations, it is proved that the bandwidth of the VCO phase noise to the output phase noise transfer function can increase up to 0.4f(REF) while maintaining phase margin. This enhanced bandwidth improves the VCO phase noise filtering strength of the PLL, leading to a superior jitter performance. The phase-domain model reveals a significant reduction in integrated jitter, compared to conventional type-I and type-II SSPLL, respectively. Furthermore, it is shown that the jitter reduction capability in the proposed loop remains robust against temperature and process variations.

This paper aims to achieve ultra-low phase noise for a voltage-controlled oscillator (VCO) through the adoption of a dual-tank configuration. The tank, based on a 1:1 transformer, incorporates an impedance scaling mechanism to reduce the equivalent parallel resistance of the tank without compromising its quality factor. Additionally, the tank provides a passive voltage gain from the drain to the gate of the core transistors, resulting in a reduction of the phase noise of the core transistors and aiding the start-up of the VCO. The tank also provides impedance peaks at the fundamental and second harmonic frequencies, leading to a flattened voltage waveform for half an oscillation cycle at the core transistors’ drains, further reducing their phase noise contribution. The VCO is fabricated in 180-nm CMOS technology. The VCO, with a die size of 0.14 mm 2 , demonstrates a state-of-the-art phase noise of -157.2 dBc/Hz at an offset frequency of 10 MHz, with the center frequency of 5.08 GHz. The oscillator’s peak Figure-of-Merit is 193.2 dBc/Hz.

This article presents a low-power and wideband variable-gain phase shifter (VGPS) designed and simulated in a CMOS 65 nm technology. It introduces a source-switching scheme for designing a variable gain amplifier (SSVGA) characterized by invariant linearity, impedance, and phase characteristics, showcasing improved gain and bandwidth compared to conventional VGAs. The current-reuse and staggered-tuning techniques are used to reduce power consumption and extend the bandwidth, respectively. The proposed VGPS enables gain tuning without the need for an additional gain tuning block, resulting in reduced chip area and sidelobe levels in phased array radar systems. The proposed VGPS, with a 5-bit resolution, achieves a 3-dB bandwidth of 18 GHz (53.5-71.5 GHz) and exhibits RMS gain error range from 0.23 to 0.5 dB and RMS phase error range from 0.54 degrees to 2.65 degrees with phase calibration based on simulation results. It achieves a peak average gain of 1.2 dB at 58.5 GHz while consuming a DC power consumption of only 5 mW with a 1.2 V power supply voltage. Moreover, it demonstrates a wide gain tuning of 20.6 dB, allowing for flexible gain adjustments.

This article studies the impact of injecting the second harmonic of the oscillation to the tail transistor, as a self-injection, in CMOS parallel LC-tank oscillators. In this scheme, the second harmonic of the oscillation is generated, delayed, and then fed back to the tail transistor. Employing the injection locking theory, closed-form formulas are derived that predicts 1/f2 phase noise arising from various noise sources in the oscillator. These formulas are validated against SpectreRF simulation results for different injection amplitudes and phases. It is shown that the phase-noise performance is improved by increasing the injection strength while the phase shift of the injected signal is set to zero. This improvement is attributed to increase oscillation amplitude and decrease phase noise factor. The amplitude and phase stability of the architecture is also analyzed in this article. Furthermore, as a case study that employs the described self-injection technique, a self-switching bias oscillator is investigated. Phase noise simulations show that the studied circuit, delivers 5 dB better phase noise, compared to the conventional class-B tail-biased oscillator.

This article proposes the theory and implementation of an even-harmonic class- $E$ CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high- $Q$ resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator’s figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class- $E$ oscillator is implemented in a 0.18- $\mu \text{m}$ CMOS technology. At 4 GHz, it exhibits a phase noise of −152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm 2 .

Based on the polyharmonic distortion (PHD) method, we present an approach to find the optimum conditions for efficient second-harmonic signal generation in millimeter-wave (mm-wave) harmonic oscillators that also maximize their DC-to-RF efficiency. These conditions include magnitude and phase of voltages at the gate and drain of the core transistors at both fundamental and second-harmonic signal components as well as the DC bias point to generate the maximum achievable second-harmonic power. We also establish that the steady-state oscillation at the fundamental frequency is a crucial criterion to obtain such conditions. The maximum achievable power and efficiency obtained from the proposed approach are independent of the harmonic oscillator topology and hence can be regarded as a reference for comparing different design techniques and structures. According to the proposed design procedure, the optimum conditions for an nMOS transistor acting as the active core of a 200-GHz harmonic oscillator are found and a second-order harmonic oscillator topology that can fulfill the optimum conditions is proposed. The oscillator is designed and fabricated in a 65-nm CMOS process and achieves peak DC-to-RF efficiency of 6.05%. The peak output power at 1.2-V supply is 2.9 dBm at 203 GHz.

Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively.

Signal sources at mm-wave and (sub-)terahertz frequencies in CMOS can be classified into two broad categories: harmonic oscillators and oscillators that are based on the frequency multiplication of fundamental sources. This paper shows that frequency-multiplier-based sources potentially have a higher dc-to-RF efficiency than do the popular harmonic oscillators in 65-nm CMOS. To improve the power efficiency of CMOS signal sources that operate near or above the cutoff frequency of the device, design factors including the harmonic current efficiency, the effective output conductance, and the passive losses should be carefully tailored. An architecture is proposed in which: 1) the core voltage-controlled oscillator is optimized to efficiently generate a strong fundamental harmonic; 2) separate class-C frequency doublers are utilized to decouple fundamental signal generation and harmonic extraction and to reduce conductance loss; and 3) doubler circuits are separately optimized to simplify the output matching and power combining network, and hence avoid long and lossy transmission lines. A circuit prototype shows a measured peak output power and dc-to-RF efficiency of 3 dBm and 2.95%, respectively.

Achieving high output power in (sub-)THz voltage-controlled oscillators (VCOs) has been a severe design challenge in CMOS technology. In this work, an architecture for coupled terahertz (THz) VCOs is presented. The architecture utilizes four coupled triple-push VCOs and combines the generated third harmonic currents using slow-wave coplanar waveguide (S-CPW) at 300 GHz. Coupling four cores increases output power, and use of S-CPW reduces the loss and increases the quality factor of the VCO tank. It is shown that using S-CPW results in ∼2.6 dB of lower loss as compared to the conventional CPW or grounded-CPW (GCPW) structures. The VCO is tuned using parasitic tuning technique and achieves 1.7% frequency tuning range (FTR). The proposed structure is designed and fabricated in a 65-nm bulk CMOS process. The measured peak output power of the 295-to-301 GHz VCO is 0.9 dBm (≈1.25 mW) at 300 GHz while consuming 235 mW (with a DC to RF efficiency of 0.52%).

Frequency synthesis at mm-wave range suffers from a severe tradeoff between phase noise (PN) and frequency tuning range (FTR). This work presents the analysis and compares the performance of fundamental-mode voltage-controlled oscillators (F-VCOs) to harmonic-mode VCOs (H-VCOs). It is shown that unlike a mm-wave F-VCO, an H-VCO can simultaneously achieve higher FTR and lower PN. An H-VCO architecture, denoted as self-mixing VCO (SMV), is presented where the VCO core generates both the first (fο) and second harmonic (2fο) and then mixes them together to obtain the desired mm-wave third-harmonic (3fο). Use of a Class-C push-push topology as the VCO core enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance, and improves PN. Compared to an F-VCO operating in a mm-wave band at a fundamental frequency that equals 3fο, the proposed SMV architecture achieves about 2× higher FTR and a better PN performance. A 52.8-62.5 GHz SMV prototype is designed and implemented in a 0.13 μm CMOS process. Measurement results show that the VCO achieves an FTR of 16.8% with a PN of -100.6 dBc/Hz at 1 MHz offset-resulting in an FTR-inclusive figure-of-merit (FoMT) of -190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply.

An analysis of the flicker noise conversion to close-in phase noise in complementary metal-oxide semiconductor (CMOS) differential inductance-capacitance (LC)-voltage controlled oscillator is presented. The contribution of different mechanisms responsible for flicker noise to phase noise conversion is investigated from a theoretical point of view. Impulse sensitivity function theory is exploited to quantify flicker noise to phase noise conversion process from both tail and core transistors. The impact of different parasitic capacitances inside the active core on flicker noise to phase noise conversion is investigated. Also, it is shown how different flicker noise models for core metal-oxide semiconductor (MOS) transistors may result in different close-in phase noise behaviors. Based on the developed analysis, design guidelines for reducing the close-in phase noise are introduced. Copyright (c) 2015 John Wiley & Sons, Ltd.

There exists a fundamental limit in improving the phase noise performance of LC-tank oscillators. Impediments to reach this limit are first discussed, and then a clipping LC VCO topology based on dual tank is presented to mitigate them. This topology can approach within 3 dB of the maximum thermodynamically achievable figure-of-merit (FoM) limit. Compared to conventional class-B/C/D/F oscillators, it is capable of reducing both close-in and far-out phase noise. As a proof of concept, a prototype 4.17-4.95 GHz VCO in a 0.13-μm CMOS process achieves a phase noise of -97 and -143 dBc/Hz at 30 kHz and 3 MHz offset, respectively.

Achieving high tuning-range and low phase-noise simultaneously in mm-wave voltage-controlled oscillators (VCO) has been a severe design challenge. Our architecture, referred herein as a self-mixing VCO (SMV), utilizes a Class-C push-push VCO topology to generate the first (f 0 ) and second harmonics (2f 0 ) and then mixes them together to obtain the desired third harmonic (3f 0 ) component. Compared to a fundamental-mode VCO operating at 3f 0 in mm-wave band, the SMV architecture achieves superior frequency tuning range (FTR) and phase-noise (PN) performance. A Class-C topology enhances the second-harmonic content to improve mixing efficiency, decreases parasitic capacitance and reduces phase noise. A 52.8-to-62.5 GHz SMV prototype is designed and implemented in a 0.13-µm CMOS process. Measurement results show an FTR of 16.8% together with a PN of −100.57 dBc/Hz at 1 MHz offset - resulting in an FTR-inclusive figure-of-merit (FOM T ) of −190.85 dBc/Hz while consuming 7.6 mW from a 1.2 V supply voltage.

This paper describes a design procedure for mm-wave voltage controlled oscillator (VCO), based on large signal behavior of oscillator transconductance. Then, a new structure of LC-VCO is presented, which utilizes a transformer feedback to enhance the transconductance of the core transistors and to cancel the undesired parasitic effects. Using a 0.18-mu m RF CMOS technology, the advantage of this VCO is examined by large signal analysis and simulation. The results illustrate improvement of 5 dB in phase-noise and 70% in tuning-range, compared to enhanced active gain conventional transformer feedback VCO. Finally, a compact layout for transformer design is proposed.

This paper presents a new low phase noise quadrature voltage-controlled oscillator (QVCO). Coupling phase shifts of 90° in conjunction with center-tapped capacitor impedance transformers are exploited to optimally couple two VCOs. DC and AC path of the switching and coupling pairs are de-coupled to allow operation in saturation for large oscillation amplitudes. The switching and coupling transistor pairs operate in class-C mode which increases the DC to RF efficiency. Also, these transistors alternate from strong inversion to accumulation region, decreasing the intrinsic device flicker noise. Simulations confirm the superiority of the proposed circuit in comparison with the prior published QVCOs in terms of phase noise performance.