In this letter, we report an approach to improve the forward bias gate reliability of Schottky gate p-GaN HEMTs. In particular, a gate layout solution, namely Gate Within Active Area (GWA), aimed at improving the high-temperature time to failure (TTF), is proposed and validated. This solution allows to avoid the exposure of the gate finger (p-GaN/metal) to the nitrogen-implantation needed for termination and isolation purposes. GWA devices feature a significantly improved gate reliability at high temperature with respect to the reference ones, under both DC and pulsed stress tests. Finally, it is demonstrated that the Schottky gate p-GaN HEMTs show a positive temperature-dependent gate TTF in a range up to 150 °C, confirming the crucial role of impact ionization on the gate failure.

In this work, a random telegraph noise (RTN) analysis has been carried out, to the best of our knowledge, for the first time to characterize the defects activated by forward-biased gate stress in GaN-HEMTs with metal/pGaN Schottky gate. The RTN signal has been measured for both gate leakage (I G ) and drain current (I D ), after each stress phase until the occurrence of the time-dependent gate breakdown. By analyzing the power spectral density (PSD) of post-stress currents, four 1/f 2 components, featuring different amplitude and time constants, were observed. In contrast, the PSD derived from fresh currents does not display segments with 1/f 2 trend. Three RTN components have been observed on both I G and I D , suggesting defect/s in the AlGaN barrier or at the AlGaN/GaN interface, whereas the fourth one showed up only on I G , could be possibly related to defects at the Schottky junction.

This letter experimentally demonstrates 1.2 kV normally-off p-GaN gate lateral high-electron-mobility transistors (HEMTs) on 200 mm diameter engineered substrates. The fabricated p-GaN gate HEMT with optimum gate-drain spacing exhibits a threshold voltage (V-th) of 3.2 V, an ON/OFF ratio of 108, low specific ON-resistance (R-on,R-sp) of 5.8 m Omega-cm(2) and hard breakdown voltage (V-bd) at 1800 V. Optimized devices also show good wafer scale uniformity ( sigma(Ron) =1.2% ) for the evaluated electrical parameters and passed on-wafer high temperature gate bias (HTGB) and reverse bias stress tests without device failures.

This article reports an in-depth analysis of the ON-resistance drift ( $\Delta {R}_{ \mathrm{\scriptscriptstyle ON}}{)}$ induced by storage/release mechanisms occurring in the buffer of GaN-on-Si power devices. The role of both stress condition (bias, temperature, and stress time) and buffer’s epi-stack composition on $\Delta {R}_{ \mathrm{\scriptscriptstyle ON}}$ has been analyzed by means of back-gating current deep-level transient spectroscopy (I-DLTS). The results reveal two competing mechanisms: 1) a faster one related to acceptor defects and sensitive to the thickness of the carbon-doped GaN back-barrier (C:GaN) and superlattice (SL) layers and 2) a slower one ascribed to hole accumulation at the C:GaN/SL interface, independent of the thickness of the epi-stack. The temperature, stress bias, and stress time dependence of such mechanisms, often overlapping, have been investigated by adopting a genetic algorithm.

In this letter, we present an extensive analysis on the role of both switching frequency (ranging from 100 kHz to 1 MHz) and duty cycle (from 10% to 90%) on the time-dependent gate breakdown of high electron mobility transistors (HEMTs) with Schottky metal to p-GaN gate. More specifically, results show how the gate lifetime of GaN HEMTs increases by reducing the frequency and the duty cycle of the stressing gate signal (VG). Such behavior is ascribed to the OFF-time, which is responsible to alter the electrostatic potential in the p-GaN layer during the rising phases of VG (from OFF- to ON-state). Findings of this analysis are useful both for further technology improvement and for GaN-based power circuit designers.

TCAD modeling of the dynamic threshold voltage shift (hysteresis) occurring under fast sweeping characterization in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) is reported, to the best of our knowledge, for the first time. Dynamic ${V}_{\text{TH}}$ hysteresis has been first experimentally characterized under different sweeping times, temperatures, and AlGaN barrier configurations. Then, TCAD simulations have been carried out, reproducing the experimental evidences and understanding the microscopic mechanisms responsible for such effect. In particular, nonlocal tunneling models implemented in Sentaurus TCAD, defined at the gate Schottky contact and assisted by traps in the AlGaN barrier layer, have been adopted and properly tuned against experiments. Results show that the dynamic ${V}_{\text{TH}}$ hysteresis is mainly caused by the time-dependent hole charging/discharging processes in the floating p-GaN layer, which are governed by the Schottky and AlGaN barrier leakage current components.

In this paper, for the first time the threshold voltage instability of 100 V rated p-GaN power HEMTs is investi-gated by combined pulsed-IV measurements and capture and emission time (CET) MAPS, by investigating a remarkable time window of 9 decades, from 1 mu s to 1000 s. After a statistical analysis to demonstrate the repeatability of the experimental results, pulsed IV characterization revealed the existence of a non-monotonic Delta VTH shift, as a function of the (positive) gate stress bias. To gain further insight on the positive threshold shift, CET MAP analysis has been carried out at different temperatures: the results provide relevant insight on the physical properties of the population of traps responsible for the VTH shift, most likely located at the AlGaN/GaN interface. In addition, the related capture and emission time-constant as a function of temperature are investi-gated, thus allowing to extract the activation energies for the trapping and de-trapping processes, and to propose a model for the trapping mechanisms.

A combined experimental/simulation analysis has been performed to study the gate reliability of GaN-HEMTs with p-type gate under pulse stress conditions. Results show that the time-dependent gate breakdown (TDGB) can be determined by two factors: i) the total ON-time during which the device is subjected to a positive gate bias before the failure; ii) the number of pulses, hence the number of switching phases from OFF- to ON-State and vice versa. The severity of the degradation ascribed to transition phases depends on the OFF-time (tOFF) and transition time (tTR = tRISE = tFALL). In particular, the shorter tOFF and tTR, the higher the Schottky junction voltage drop and the current peak during the switching phase, respectively. The higher voltage drop is ascribed to the semi-floating potential of the p-GaN layer.

Compact modeling of charge trapping processes in GaN transistors is of fundamental importance for advanced circuit design. The goal of this article is to propose a methodology for modeling the dynamic characteristics of GaN power HEMTs in the realistic case where trapping/detrapping kinetics are described by stretched exponentials, contrary to ideal pure exponentials, thus significantly improving the state of the art. The analysis is based on: 1) an accurate methodology for describing stretched-exponential transients and extracting the related parameters and 2) a novel compact modeling approach, where the stretched exponential behavior is reproduced via multiple RC networks, whose parameters are specifically tuned based on the results of 1). The developed compact model is then used to simulate the transient performance of the HEMT devices as a function of duty cycle and frequency, thus providing insight on the impact of traps during the realistic switching operation.

In this article, we present an in-depth high-temperature analysis of the long-term gate reliability in GaN-based power high-electron-mobility transistors (HEMTs) with p-type gate. Three different isolation process options, aimed at improving the time-dependent gate breakdown (TDGB), are proposed and compared by means of constant voltage stress tests performed at different forward gate biases, temperatures, and geometries. In particular, depending on the gate bias and temperature, the breakdown event may occur along the active gate area or through the isolation region. The results show different voltage dependency for such two different failure locations; therefore, two field-acceleration fitting models are needed for the estimation of lifetime. Furthermore, the gate time-to-failure (TTF) shows a non-monotonous temperature dependency at given gate bias. More specifically, a positive and a negative T-derivatives are observed at relatively low and high temperatures, respectively, which are related to active gate area and isolation region failure, respectively.

In this article, we present an extensive investigation of the time-dependent drain breakdown occurring in GaN-on-Si power HEMTs with p-GaN gate under long-term OFF-state stress. In particular, the time-dependent breakdown induced by high-temperature-reverse-bias stress is investigated as a function of different process and structural variations. Main results demonstrate that, by varying the gate-to-drain distance (LGD) and the field plates configuration, the physical location of failure changes as well. If LGD is relatively short (3 μm), the time-dependent breakdown occurs through the GaN channel layer between drain and source. In this case, a thinner GaN layer significantly improves the device robustness to long-term OFF-state stress. If LGD is relatively long (≥ 4 μm), the failure occurs between the two-dimensional electron gas (2DEG) and the source field plates. In this second case, the GaN layer thickness and LGD have no significant impact on the time-dependent breakdown, whereas the field plate lengths can be optimized to reduce the area exposed to high electric fields, hence limiting the probability of failure. Finally, the role of the AlGaN barrier layer has been analyzed as well. If LGD = 3 μm, a thinner AlGaN layer is preferred, whereas if LGD ≥ 4 μm, a thicker layer with lower aluminum content gives rise to longer time to breakdown under OFF-State stress.

In this paper the reliability of the vertical GaN-on-Si stack for lateral p-GaN HEMTs dedicated to low-voltage applications is discussed in detail by comparing wafers with different buffer thicknesses and growth condition of the AlN nucleation layer. The vertical robustness and the time-dependent vertical breakdown will be investigated in detail, demonstrating that the buffers with reduced thickness are suitable for 100 V applications. Moreover, the voltage drop on the different layers of the vertical stack will be extracted at the breakdown, and a model able to explain the degradation of the vertical stack will be proposed.

In this paper, we present an in-depth study of the gate leakage mechanisms and correlated breakdown of GaN-based power HEMTs with p-GaN gate, controlled by a Schottky metal/p-GaN junction. A detailed investigation of the process split and geometry dependency is done. From this study, we propose that a parasitic sidewall transistor is present, which is the cause for degradation in the p-GaN gate. The sidewall leakage has been substantiated by TCAD simulation and also by a novel method consisting of EBIC measurements directly applied on the cross section of a p-GaN gate. Based on this analysis we performed a process modification, which has led to a significant improvement in terms of gate reliability.

In this article, we present an analysis of the gate degradation induced by long-term forward gate stress in GaN-based power HEMTs with p-type gate, controlled by a Schottky metal-retracted/p-GaN junction. In particular, time-dependent gate breakdown and threshold voltage instability are investigated as function of different geometries, gate biases, and temperatures. The introduction of a gate metal retraction (GMR) process step improves the device lifetime because it suppresses the onset of the leakage current flow occurring at the gate edges for relatively high gate voltage. However, biasing GMR p-GaN HEMT at V-G > 8 V and T > 80 degrees C, a new degradation mechanism shows up, possibly altering the lifetime even at low V-G operation. Main results in this article demonstrate that although at high V-G and high T, a localized degradation effect ascribed to the device isolation region is responsible for time-dependent gate breakdown, thanks to GMR higher operating voltages compatible with ten-year continuous operation is attained. Finally, the longer device lifetime at moderate V-G values brought by GMR allows evaluating the threshold voltage instability for long stress times (approximate to 112 h) at relatively high V-G and high T, leading to the observation of a saturation of the long-term positive threshold voltage shift and providing additional information about the underlying physical degradation mechanisms. Overall, the saturated 0.65-V Delta V-TH under worst-case condition (V-G = 7 V at 150 degrees C, i.e., corresponding to ten-year lifetime) reveals a reliable and fairly stable technology with respect to forward gate stress.

We report the first comprehensive research about GaN power integrated circuits (ICs) on GaN-on-SOI (silicon-on-insulator). Specific stepped (Al)GaN superlattice buffer and highly robust deep trench isolation are developed. Various components including HEMT, metal-insulator-metal (MIM) capacitor, Schottky barrier diode (SBD), two-dimensional electron gas (2DEG) resistor, and resistor-transistor logic (RTL) are co-integrated, compatible with the p-GaN technology. Based on these achievements, 200 V GaN HEMT with integrated driver shows an extraordinary switching performance. A 48V-to-1V single-stage buck converter is realized using a GaN half-bridge with integrated on-chip drivers. Further, an all-GaN buck converter containing a smart control pulse-width modulation (PWM) circuit, dead-time control, drivers, and half-bridge is successfully designed using the GaN IC platform process design kit (PDK).

This paper describes our most advanced results in the field of GaN-HEMT degradation, with focus on power devices. We discuss three main aspects: (i) the first part of the paper analyzes the dependence of breakdown voltage on substrate and buffer properties, by reporting the results obtained on wafers with different substrate resistivities and superlattice thickness. (ii) the second part of the paper demonstrates the existence of time-dependent breakdown of GaN buffer submitted to high vertical stress, and describes the related process. (iii) in the third part of the paper, we focus on the role of hot-electrons in limiting the dynamic performance of the devices. We demonstrate that the exposure to hard switching transitions may lead to an increase in dynamic R-on. This effect is ascribed to the presence of hot electrons, which was verified by means of electroluminescence measurements.

In this paper, we present an experimental analysis of the degradation induced by positive bias temperature instability stress in GaN-based power high electron mobility transistors with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, the role of the aluminum content (Al%) in the AlGaN barrier layer on the threshold voltage degradation is investigated by means of constant voltage stress measurements. This has been performed for different process conditions with varying Al content. Main results in this paper demonstrate that when a relatively large positive bias is applied on the gate, two competing trapping mechanisms take place in the AlGaN barrier layer or at the p-GaN/AlGaN interface causing ${V}_{\text {TH}}$ instability. First, an aluminum independent hole trapping mechanism, caused by elastic tunneling from p-GaN valence band (2-D hole gas), leads to a relatively short-time and recoverable negative ${V}_{\text {TH}}$ shift. In the second step, defect creation occurs. These additional defects are filled with electrons and cause a permanent or slowly recoverable positive ${V}_{\text {TH}}$ degradation. The amount of defect creation was dependent on the Al% in the barrier.

Within this paper we investigate the degradation of GaN-HEMTs with p-GaN gate submitted to stress at forward gate bias. We studied the effect of both constant-voltage stress and short-pulse stress (induced by TLP, Transmission Line Pulser); devices having three different Mg-doping levels (ranging from 2.1 . 10(19)/cm(3) to 2.9 . 1019/cm(3)) were used for the study. We demonstrated the existence of two different degradation mechanisms, depending on the stress conditions: (i) when submitted to TLP stress (100 ns pulses with increasing amplitude), the failure occurs through a field driven process, i.e. the breakdown of the metal/p-GaN Schottky junction, which is reversely biased when the gate is at positive voltage. Failure voltage decreases with increasing Mg doping, since higher acceptor levels result in a higher electric field. (ii) Conversely, during constant-voltage stress, the long-term stability is undermined by a current-driven process, namely the accumulation of positive charges at the p-GaN/AIGaN interface, which promotes an increase of the leakage current, first gradual and then catastrophic. Increasing Mg-concentration in the p-GaN results in a reduction of the gate leakage at high forward gate bias. As a consequence, devices with higher Mg doping have long TTF (more than two orders of magnitude with respect to the samples with lower Mg doping). (C) 2017 The Authors. Published by Elsevier Ltd.