GaN/InGaN microLEDs are a very promising technology for next-generation displays. Switching control transistors and their integration are key components in achieving high-performance, efficient displays. Monolithic integration of microLEDs with GaN switching devices provides an opportunity to control microLED output power with capacitive (voltage)-controlled rather than current-controlled schemes. This approach can greatly reduce system complexity for the driver circuit arrays while maintaining device opto-electronic performance. In this work, we demonstrate a 3-terminal GaN micro-light emitting transistor that combines a GaN/InGaN blue tunneling-based microLED with a GaN n-channel FET. The integrated device exhibits excellent gate control, drain current control, and optical emission control. This work provides a promising pathway for future monolithic integration of GaN FETs with microLED to enable fast switching, high-efficiency microLED display and communication systems.

Activation of ion‐implanted p‐type dopants in gallium nitride has demonstrated great progress utilizing high pressures to enable novel and traditional device architectures; however, such conditions consistently exhibit anomalously enhanced diffusion up to several microns in very short periods of time for device relevant concentrations. Here, this diffusion is shown to be modulated by unintentional hydrogen content within the anneal ambient and thus controllable by inclusion of a high‐temperature hydrogen getter. Furthermore, diffusion is also shown to be greatly suppressed using co‐implanted oxygen at low concentrations while simultaneously maintaining characteristics of p‐type material in photoluminescence. Subsequently, after annealing at 1300 °C for 30 min in 3.8 kbar of nitrogen pressure, the magnesium concentration in the diffusion tail is suppressed by 28% at 1–1.5 μm in depth using a hydrogen getter alone, which reduces hydrogen uptake by 45% and fully suppressed at >1 μm in depth using co‐implantation alone and further reduced with concurrent use of a hydrogen getter. Co‐implantation alone reduces the in‐diffused magnesium dose by 60% compared to reference samples.

Defect mitigation of electronic devices is conventionally achieved using thermal annealing. To mobilize the defects, very high temperatures are necessary. Since thermal diffusion is random in nature, the process may take a prolonged period of time. In contrast, we demonstrate a room temperature annealing technique that takes only a few seconds. The fundamental mechanism is defect mobilization by atomic scale mechanical force originating from very high current density but low duty cycle electrical pulses. The high-energy electrons lose their momentum upon collision with the defects, yet the low duty cycle suppresses any heat accumulation to keep the temperature ambient. For a 7 x 105 A cm-2 pulsed current, we report an approximately 26% reduction in specific on-resistance, a 50% increase of the rectification ratio with a lower ideality factor, and reverse leakage current for as-fabricated vertical geometry GaN p-n diodes. We characterize the microscopic defect density of the devices before and after the room temperature processing to explain the improvement in the electrical characteristics. Raman analysis reveals an improvement in the crystallinity of the GaN layer and an approximately 40% relaxation of any post-fabrication residual strain compared to the as-received sample. Cross-sectional transmission electron microscopy (TEM) images and geometric phase analysis results of high-resolution TEM images further confirm the effectiveness of the proposed room temperature annealing technique to mitigate defects in the device. No detrimental effect, such as diffusion and/or segregation of elements, is observed as a result of applying a high-density pulsed current, as confirmed by energy dispersive x-ray spectroscopy mapping.

We report non-planar regrowth of InGaN quantum wells on triangular InGaN buffer layers grown on sub-200nm-wide GaN ridges. Photo-pumped internal quantum efficiencies above 20% at yellow wavelengths hold promise for semiconductor laser gain regions.

Vertical gallium nitride (GaN) power devices continue to garner interest in multiple power conversion applications requiring a medium-voltage (1.2 – 20 kV) capability. Currently, silicon carbide (SiC) is addressing this voltage range, however, with a comparable critical electric field and superior mobility, GaN is expected to offer advantages in applications where fast switching and avalanche breakdown response times are desired. While uses in electric vehicles, solid-state transformers, and renewable energy conversion are being actively explored, the potential of a vertical GaN device for electric grid protection in the form of an electromagnetic pulse arrestor is a unique proposition that requires very fast transient capabilities (<1 µs pulse widths with rise-times on the order of 10 ns). However, vertical GaN devices are significantly less mature than present SiC offerings. Specifically, low-doped, thick epitaxial growth of GaN via metal-organic chemical vapor deposition (MOCVD) still presents many challenges, and advancements in processing, manufacturability, and failure analysis are needed. In this work, we describe our efforts to address the above issues and advance the state-of-the-art in vertical GaN PN diode development. We have successfully demonstrated an MOCVD-grown, 50 µm thick, low-doped (<10 15 cm -3 ) drift region on a GaN substrate that was processed into relatively large-area (1 mm 2 ) PN diodes capable of achieving a 6.7 kV breakdown. Temperature-dependent breakdown was observed, consistent with the avalanche process. The devices consisted of a 4-zone step-etched junction termination extension (JTE), where the breakdown region was visualized via electroluminescence (EL) imaging. Ongoing work aims to scale the current capability of the medium-voltage diodes through a parallel interconnect design that negates defective or poor performing diodes. Further investigation of edge termination structures was explored using a bevel approach, where we studied the relationship between the bevel angle and p-doping. It was found that a very shallow angle of only 5° accompanied by a 500 nm p-region consisting of 3×10 17 cm -3 Mg concentration resulted in a consistent 1.2 kV breakdown for an 8 µm thick, 1.6×10 16 cm -3 doped drift region. EL imaging confirmed uniform breakdown, and temperature dependence was demonstrated. The bevel approach was then implemented on a diode structure with a 20 µm thick drift region capable of 3.3 kV breakdown, where an unclamped inductive switching (UIS) test was performed to evaluate the impact of a field plate design on avalanche uniformity and ruggedness. A parallel effort to establish a foundry process for vertical GaN devices has been underway. Initially, this focus was on comprehensive studies of GaN wafer metrology using capacitance-voltage (C-V) mapping, optical profilometry, and x-ray diffraction (XRD) mapping. A machine learning algorithm was implemented to identify defective regions and produce a yield prediction for each GaN wafer prior to processing. A hybrid edge termination structure consisting of implanted guard rings (GR) and JTEs was developed in coordination with a controlled experiment that varied the anode thickness, and therefore the remaining p-GaN after implantation. It was observed that thinner p-GaN regions under the JTE/GR region resulted in a significant (>100x) reduction in leakage current under reverse-bias conditions. This process has resulted in 1.2-kV-class devices with up to 18 A forward current for a 1 mm 2 device with a specific on-resistance of 1.2 mOhm-cm 2 . The foundry effort has since been extended to 3.3-kV-class devices that utilize 25 µm thick drift layers with ~2-4×10 15 cm -3 doping. These devices have demonstrated up to 3.8 kV breakdown with leakage currents <1 nA up to 3 kV. More than 40 wafers have been processed to date, resulting in >20,000 devices. Statistical variations in I-V and C-V characteristics will be discussed. Packaging process development and analysis are underway to develop electrical stress procedures and identify fundamental failure mechanisms. Finally, a pulse arrested spark discharge (PASD) setup, capable of up to 15 kV pulsed operation in 100 V steps, was implemented to quantify the time response of avalanche breakdown. Initial results on a packaged 800 V device showed a ~1 ns response time during breakdown, which reinforces the potential EMP grid protection applicability. This work was supported by the ARPA-E OPEN+ Kilovolt Devices Cohort directed by Dr.Isik Kizilyalli. Sandia National Laboratories is a multi-mission laboratory managed and operated by National Technology & Engineering Solutions of Sandia, LLC, a wholly owned subsidiary of Honeywell International Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA0003525. This paper describes objective technical results and analysis. Any subjective views or opinions that might be expressed in the paper do not necessarily represent the views of the U.S. Department of Energy of the United States Government.

Foundry compatible vertical GaN PiN diodes were fabricated. The devices investigated in this work are based on 8 um drift layer thickness to achieve ∼1.2 kV of voltage blocking. Three different anode doping levels were fabricated on three wafers with the same p-layer thickness, and planar hybrid edge termination. The moderate anode doping level of 1 × 10 18 cm −3 has achieved the highest breakdown voltage of 1.2 kV and its temperature-dependent breakdown behavior proved an avalanche behavior. Furthermore, our electroluminescence displayed the breakdown at the edge of the anode. Our simulation results imply an improvement in the field management with moderate anode doping.

To improve the manufacturing process of GaN wafers, inexpensive wafer screening techniques are required to both provide feedback to the manufacturing process and prevent fabrication on low quality or defective wafers, thus reducing costs resulting from wasted processing effort. Many of the wafer scale characterization techniques—including optical profilometry—produce difficult to interpret results, while models using classical programming techniques require laborious translation of the human-generated data interpretation methodology. Alternatively, machine learning techniques are effective at producing such models if sufficient data is available. For this research project, we fabricated over 6000 vertical PiN GaN diodes across 10 wafers. Using low resolution wafer scale optical profilometry data taken before fabrication, we successfully trained four different machine learning models. All models predict device pass and fail with 70–75% accuracy, and the wafer yield can be predicted within 15% error on the majority of wafers.

Defect origins and their propagation behavior were investigated in 25 μm thick homo-epitaxial GaN layers grown on ammono-thermal and void-assisted separation (VAS) substrates using multi-vector x-ray topography in both transmission and reflection geometries. Complex inclusions were identified and their microstructure was analyzed. Additionally, generation of threading dislocation clusters during epitaxial growth is analyzed. Various defects are delineated from the substrate vs epitaxial layers. Growth on the ammono-thermal substrate led to less defective and flatter epitaxial layers compared to the growth on the VAS substrate. Determining the origins and microstructure of defects is crucial toward developing defect mitigation strategies for reliable GaN devices.

Vertical power devices require significant attention to their edge termination designs to obtain higher breakdown voltages without substantial increase in ON-state resistance. A simple edge termination structure for a GaN p-n diode is proposed, comprising a full layer lightly doped p-type GaN region underneath the higher doped ${p} +\!+$ contact layer. A TCAD model of the device is developed, and removal of the portions of ${p}$ ++ cap outside of the device active area in simulations is shown to increase the device blocking voltage capability. It causes the depletion width to increase in the lightly doped p-type layer and allows it to act similar to a junction termination extension (JTE). These predictions are validated empirically, resulting in a 52% measured increase in breakdown capability after selective removal of the ${p}$ ++ cap. This simple edge termination technique can be formed with only a single low-energy nitrogen implant or etching procedure, greatly increasing its manufacturability over more complex structures. Design optimization studies are pursued in TCAD to determine optimal parameter values for further improving breakdown performance. It is shown that the proposed edge termination technique can be employed to produce future high voltage vertical GaN devices without a significant gain in ON-state resistance and with wide tolerance to process variations.

To improve the manufacturing of vertical GaN devices for power electronics applications, the effects of defects in GaN substrates need to be better understood. Many non-destructive techniques including photoluminescence, Raman spectroscopy and optical profilometry, can be used to detect defects in the substrate and epitaxial layers. Raman spectroscopy was used to identify points of high crystal stress and non-uniform conductivity in a substrate, while optical profilometry was used to identify bumps and pits in a substrate which could cause catastrophic device failures. The effect of the defects was studied using vertical P-i-N diodes with a single zone junction termination extention (JTE) edge termination and isolation, which were formed via nitrogen implantation. Diodes were fabricated on and off of sample abnormalities to study their effects. From electrical measurements, it was discovered that the devices could consistently block voltages over 1000 V (near the theoretical value of the epitaxial layer design), and the forward bias behavior could consistently produce on-resistance below 2 mΩ cm2, which is an excellent value considering DC biasing was used and no substrate thinning was performed. It was found that high crystal stress increased the probability of device failure from 6 to 20%, while an inhomogeneous carrier concentration had little effect on reverse bias behavior, and slightly (~ 3%) increased the on-resistance (Ron). Optical profilometry was able to detect regions of high surface roughness, bumps, and pits; in which, the majority of the defects detected were benign. However a large bump in the termination region of the JTE or a deep pit can induce a low voltage catastrophic failure, and increased crystal stress detected by the Raman correlated to the optical profilometry with associated surface topography.

Impact ionization coefficients play a critical role in semiconductors. In addition to silicon, silicon carbide and gallium nitride are important semiconductors that are being seen more as mainstream semiconductor technologies. As a reflection of the maturity of these semiconductors, predictive modeling has become essential to device and circuit designers, and impact ionization coefficients play a key role here. Recently, several studies have measured impact ionization coefficients. We dedicated the first part of our study to comparing three experimental methods to estimate impact ionization coefficients in GaN, which are all based on photomultiplication but feature characteristic differences. The first method inserts an InGaN hole-injection layer, the accuracy of which is challenged by the dominance of ionization in InGaN, leading to possible overestimation of the coefficients. The second method utilizes the Franz–Keldysh effect for hole injection but not for electrons, where the mixed injection of induced carriers would require a margin of error. The third method uses complementary p–n and n–p structures that have been at the basis of this estimation in Si and SiC and leans on the assumption of a constant electric field, and any deviation would require a margin of error. In the second part of our study, we evaluated the models using recent experimental data from diodes demonstrating avalanche breakdown.

The III-nitride semiconductors are attractive for on-chip, solid-state vacuum nanoelectronics, having high thermal and chemical stability, low electron affinity, and high breakdown fields. Here we report top-down fabricated, lateral gallium nitride (GaN)-based nanoscale vacuum electron diodes operable in air, with ultra-low turn-on voltages down to ~0.24 V, and stable high field emission currents, tested up to several microamps for single-emitter devices. We present gap-size and pressure dependent studies which provide insights into the design of future nanogap vacuum electron devices. The vacuum nanodiodes also show high resistance to damage from 2.5 MeV proton exposure. Preliminary results on the fabrication and characteristics of lateral GaN nano vacuum transistors will also be presented. The results show promise for a new class of robust, integrated, III-nitride based vacuum nanoelectronics.

Vertical gallium nitride (GaN) p-n diodes have garnered significant interest for use in power electronics where high-voltage blocking and high-power efficiency are of concern. In this article, we detail the growth and fabrication methods used to develop a large area (1 mm 2 ) vertical GaN p-n diode capable of a 6.0-kV breakdown. We also demonstrate a large area diode with a forward pulsed current of 3.5 A, an 8.3- $\text{m}\boldsymbol \Omega \cdot {\text{cm}}^{2}$ differential specific ON-resistance, and a 5.3-kV reverse breakdown. In addition, we report on a smaller area diode (0.063 mm 2 ) that is capable of 6.4-kV breakdown with a differential specific ON-resistance of 10.2 $\text{m}\boldsymbol \Omega \cdot {\text{cm}}^{2}$ , when accounting for current spreading through the drift region at a 45° angle. Finally, the demonstration of avalanche breakdown is shown for a 0.063-mm 2 diode with a room temperature breakdown of 5.6 kV. These results were achieved via epitaxial growth of a 50- $ \mu \text{m}$ drift region with a very low carrier concentration of $< 1\times10$ 15 cm −3 and a carefully designed four-zone junction termination extension.

GaN research is important to the development of next generation power conversion technology because its large Baliga figure of merit GaN gives it the potential to outperform SiC. Presently, commercialized GaN technology is based on lateral high electron mobility transistors (HEMTs); however, large areas would be required for high voltage applications thus there is motive to switch to vertical GaN. Current GaN substrate manufacturing technology is known to produce inconsistent quality with a varying concentration of defects. These defects are known to cause catastrophic device failure, thus there is motive to develop quick, non-destructive techniques to predict the quality of the wafer before undergoing the expensive fabrication process. This talk focuses on using data science and machine learning to predict the quality of the diodes. This work demonstrated that Raman spectroscopy can be used to detect high crystal stress points, which strongly correlates with an increased leakage current. Optical profilometry images can be used to detect defects that cause catastrophic failures; however, the presence of benign defects makes it difficult to predict the device quality using a simple algorithm. Thus, a machine learning algorithm relate optical profilometry images to device performance of subsequently processed device. The results showed that this algorithm was 91% accurate at predicting the forward bias behavior of devices, and it is possible that the devices it could accurately predict failures due to device processing errors. This work was supported by the Office of Naval Research.

GaN vertical PiN diodes with different anode thicknesses were fabricated on three native GaN wafers with the same p-layer doping concentrations, and planar hybrid edge termination. The breakdown behavior in terms of the breakdown voltage and the electroluminescence were studied as functions of the anode thickness. A repeatable avalanche breakdown and highest breakdown voltage were measured with the thinnest anode of 300 nm and with the thinnest edge termination region. This indicates the efficacy of the nitrogen-implanted hybrid edge termination design that comprises of junction termination and guard rings hybrid design. As the anode thickness increases, the edge termination thickness increases, and the devices exhibit lower breakdown voltages and less robust breakdown characteristics, often destructive. From this study, we also conclude that a very high p-layer doping of 2 × 1019 cm−3 is not s practical doping level, because it is too sensitive to the edge termination thickness.