Most analog compute-in-memory (ACiM) works only focus on the multiple-accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-memory MAC with hybrid capacitor ladders. Then, a sparsity-aware R-2R DAC and an embedded SAR-ADC that reuses the capacitor ladders in the MAC are introduced to reduce the conversion overhead. Two on-chip AF schemes are included to further improve efficiency. Finally, differential signal path offers first-order PVT cancellation that improves computing accuracy and reduces the need for calibration.

Frequent data conversion in analog compute-in-memory (ACiM) reduces the benefits obtained by analog computing. This paper proposes an efficient signed 8b multiple-accumulate (MAC) unit with hybrid differential capacitor ladders. Then a sparsity-aware DAC and an embedded SAR-ADC are introduced to lower the data conversion overhead. Finally, two activation functions (AFs) are included to further improve efficiency: 1) ReLU is realized by SAR-ADC LSB skipping; 2) tanh is built with analog buffers to bypass data converters.

Fast, low-power ADCs with $\sim 5 -6$ effective bits of resolution are a key element of 50+Gb/s links, which often use DSP-based equalization to compensate for high channel loss and high-order modulation schemes (e.g. PAM-4) to push link speed. Voltage-domain SAR ADCs are commonly time-interleaved (TI) to reach these speeds [1–2] but often require calibration-intensive techniques such as multi-comparator loop-unrolling [2] or pipelining to increase sub-ADC speed beyond $\sim 1$ GS/s, which is critical to reduce area and improve bandwidth by lowering capacitive input load. Time-domain ADCs can offer a fast ($\gt3{\mathrm{GS/s}}$), energy efficient [3] alternative well-suited to deeply scaled CMOS implementation. However, reliance on matched gate delays instead of capacitive weights either requires power-hungry phase interpolation or increases sensitivity to PVT variation and mismatch, which is detrimental to TI ADCs that need robust performance from all sub-ADCs. Hybrid voltage and time domain $( \mathrm{V}+\mathrm{T})$ ADCs [4–6] can bring the speed advantages of time-domain operation to voltage-domain ADCs. As in [4–5], in this work a voltage-to-time converter (VTC) acts as a high-speed buffer and a time-to-digital converter (TDC) operates in parallel with a time-to-voltage converter (TVC) to generate a coarse signal estimate to speed up a single-comparator SAR ADC. To improve upon prior art, this work uses the hybrid architecture to optimize the TI ADC floorplan and enhances reliability through (1) a VTC with common-mode input voltage tracking and (2) a merged flash TDC+TVC to guarantee TDC monotonicity with low added power. The 22nm CMOS prototype consumes 76mW at 40GS/s including input and reference buffers and achieves 32.3dB SNDR with a 20GHz input, for 57fJ/step ${\mathrm {FoM_{W}}}$.

High-speed links require fast, moderate resolution analog-to-digital converters (ADCs) with low power to maximize efficiency. Hybrid voltage and time (V+T) ADCs can combine the speed benefits of time-domain conversion with the reliability of conventional voltage-domain ADCs. This letter demonstrates 1) how the V+T architecture can simplify time interleaving implementation and 2) highlights two methods for improving V+T sub-ADC robustness: a) a voltage-to-time converter (VTC) with common-mode input voltage tracking and b) a merged time-to-voltage and flash time-to-digital converter. This is demonstrated in a 0.103-mm(2) 22-nm CMOS prototype that consumes 76 mW and gives 32.3-dB SNDR with a Nyquist input at 40 GS/s, for 57-fJ/step FoMw.

Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of $\sim $ 1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35–133 $\times $ improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.

Recent work has shown the ability of mm-wave (30 to 100GHz) and sub- THz (100 to 300GHz) receivers to support large bandwidths needed to meet growing data-rate demands in a variety of applications, from dielectric waveguide [1] to wireless [2], [3] links. Unfortunately, prior art either excludes the integration of critical receiver blocks (e.g. PLL, ADC) or contains complete but power-hungry LO generation [2]. A critical challenge in demonstrating sub-THz receivers with an integrated ADC is the limited availability of process nodes that provide efficient performance for both RF and mixed-signal/digital circuits simultaneously. This work presents a D-band (140GHz) receiver (RX) which integrates the RX front-end (RXFE) with PLL and ADC in a 22nm FinFET process co-optimized for RF and digital performance. The RX achieves a maximum data-rate of 128Gb/s with a total efficiency of 1.95pJ/b.

Compute-in-memory (CiM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, the tradeoff between energy efficiency and computing precision plagues most CiM implementations, and the low precision imposes a major limitation on CiM’s ability to support practical computational workloads. In this article, a static random access memory (SRAM)-based analog CiM macro is presented with the Intel 22FFL process. By introducing a 1-to-2 ratioed capacitor ladder (C-2C)-based charge domain computing scheme, the proposed CiM prototype chip demonstrates a maximum of 2k multiply-accumulate (MAC) operations in one clock cycle and achieves 32.2-TOPS/W peak power efficiency with 8-bit precision in both input activation and weight while ensuring accurate on-chip matrix–vector multiplications (MVMs) with a computation error less than 0.5%. A 4.0-TOPS/mm2 peak area efficiency is attained by adopting a local weight multiplexing scheme with a 9T SRAM cell, which improves the memory density and reduces the need to refresh the weight stored in the SRAM array. A variety of analog impairment factors, including parasitics, mismatch, and noise, were analyzed to guarantee a sufficiently high multibit linearity. The proposed passive analog computing mechanism ensures the computation accuracy over process–voltage–temperature (PVT), with the measured MVM error deviation of less than 1% over PVT variations.

This article presents a ultra-wideband (UWB)-based wireless transceiver (TRX) in a reconfigurable frequency-division duplexing (FDD) wireless network for short-range multicast applications. The TRX operates at the 7–10-GHz band, adopts a digital-process-friendly architecture, and delivers up to 2-Gb/s data rate in 500-MHz channel bandwidth. The measured power consumption is 19.8 mW at the 8-GHz channel, resulting in a best-in-class energy efficiency of 9.9 pJ/b for sub-10-GHz wireless TRXs. The TRX outputs −5.5-dBm power and achieves −67.5-dBm sensitivity at 1 Gb/s. Having a coherent TRX architecture, it can tolerate self-interference during FDD operation with 1-dB receiver de-sensitization and close-in −26-dBm Wi-Fi blockers with 3-dB de-sensitization.

Compact, high-bandwidth analog-to-digital converters (ADCs) with moderate resolution are a critical building block in high-speed communication links. In this work, a hybrid time and voltage domain ADC is presented that uses a single high-speed voltage-to-time converter (VTC) as a high-bandwidth sampling buffer for a four-way time-interleaved successive approximation (SAR) ADC. Time-domain encoding also enables a low-power 3b SAR assist time-to-digital converter (TDC) to enhance SAR speed with minimal calibration. A 0.0045 mm2 prototype fabricated in 22 nm fin field-effect transistor (FinFET) CMOS provides 13 GHz effective resolution bandwidth (ERBW) and consumes 6.0 mW with a Nyquist signal-to-noise-and-distortion ratio (SNDR) of 38 dB at 3.8 GS/s, for 24.4 fJ/step Walden FoM.

This work presents a ${D}$ -band (110–170 GHz) receiver (RX) with integrated analog-to-digital converter (ADC) and phase-locked loop (PLL). The receiver front end (RXFE) consists of a coupled-line-based Guanella balun matching network, 140-GHz low-noise amplifier (LNA), and Cherry–Hooper (CH) amplifier providing $>$ 20-GHz baseband bandwidth. A quadrature PLL provides I/Q local oscillator (LO) signals for down-conversion. Two 32-GS/s hybrid voltage- and time-domain ADCs digitize the RXFE output. The fully integrated 22-nm FinFET CMOS prototype achieves a peak data rate of 128 Gb/s using 16-QAM modulation with –15.2-dB EVM and consumes 246 mW for 1.95-pJ/b efficiency. The stand-alone RXFE without ADC provides 160-Gb/s data rates with –16.4-dB EVM and consumes 166 mW for 1.04-pJ/b efficiency.

Increasing demand for data-rate is pushing wireless links to operate at mm-wave (30 to 100GHz) and subTHz (100 to 300GHz) carrier frequencies, where larger available bandwidth can be leveraged to increase capacity. Novel radio architectures and process scaling are enabling transceiver implementations in low-cost CMOS technologies for commercial applications. Recent publications have demonstrated mm-wave/subTHz transceivers targeting 100+ Gb/s operation with improved efficiencies. Applications range from short/long-range wireless [1] to medium-range links over plastic waveguide [2] with transmitter data-rates up to 140Gb/s and efficiencies of 5 to 10pJ/b. This paper presents a fully integrated D-band transmitter (TX) achieving 160Gb/s at ~ 1 pJ/b efficiency in 22nm FinFET technology. In contrast to many prior works, this performance is achieved while integrating all critical blocks, from bits to RF.

This paper presents a sub-10GHz wireless transceiver for short-range multicast applications in a reconfigurable FDD wireless network. The transceiver adopts a digital-process-friendly architecture and can deliver up to 2Gb/s data rate in a 500MHz channel bandwidth with 19.8mW power consumption and 9.9pJ/b energy efficiency. Being a coherent transceiver, it outputs -5.5dBm power, achieves -67.5dBm sensitivity at 1Gb/s and 1dB de-sensitization during FDD operation while tolerating -26dBm close-in Wi-Fi blockers.

This work presents a fully integrated 140-GHz transmitter (TX) achieving a data rate of 160 Gb/s with ~1-pJ/b efficiency in the 22-nm Intel FinFET technology. The TX leverages a wideband radio frequency digital to analog converter (RF-DAC) architecture with embedded 4:1 multiplexer, and it is integrated with a sub-sampling quadrature phase-locked loop (PLL), frequency tripler, local oscillator (LO) buffers, wideband two-stage power amplifier (PA), and on-chip SRAM/pseudorandom binary sequence (PRBS) for high-speed data generation. The TX achieves 120/160-Gb/s 16 quadratic-amplitude modulation (QAM) with −19/−17-dB error vector magnitude (EVM) at an output power of +1.5/+0.8 dBm.

A 2.4 mW, 1ps RMS jitter temperature stable 38.4 MHz Thin

This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.

An Impedance Guided Chirp Injection (IGCI) oscillator-based fast startup technique is proposed in this work demonstrating startup time between 5 and 100 $\mu \text{s}$ across a wide range of oscillator frequencies. The IGCI technique can efficiently detect the resonance frequency of the crystal and provide energy injection for fast crystal startup. The simplicity of the implementation of the IGCI circuitry enables easy porting across technology nodes and interfacing with different oscillator topologies. Compared to previous negative resistance boosting or open-loop injection techniques, the proposed IGCI achieves both faster startup and lower injection power which reduces the overall startup energy. A test chip is fabricated in Intel 22FFL technology and the measurements are performed using 38.4 MHz crystal achieving ~2.6 $\times $ faster startup than normal startup (with same biasing, load cap) without any injection. Extensive measurements are performed across different temperatures and multiple startup occurrences.

This work presents a hybrid time and voltage domain ADC that uses a single high-speed voltage-to-time converter (VTC) as a sampling buffer for interleaved SAR ADCs to enhance bandwidth and remove timing skew mismatch. Time-domain encoding also allows a low-power 3b assist TDC to enhance SAR speed with minimal calibration. At 3.8 GS/s, the 0.0045 mm 2 22nm FinFET prototype with 13 GHz ERBW consumes 6.0 mW with a Nyquist SNDR of 38 dB for 24.4 fJ/step FoM.

In recent years, Neural Networks (NNs) have achieved tremendous success in a variety of fields, such as computer vision, natural language processing, speech recognition, autonomous driving, and healthcare [1] –[4]. However, conventional NNs rely heavily on large, labeled training datasets, which can lead to overfitting and overconfident decision making (especially when faced with unfamiliar, out-of-distribution inputs) [1] –[4]. Unlike conventional NNs, the weights of Bayesian Neural Network (BNNs) are represented by probability distributions, providing a mathematical framework to quantify the uncertainties in a model’s final prediction [3]. These uncertainty estimates allow BNNs to mitigate overfitting issues, enable training with smaller datasets, and help increase overall model accuracy through the implicit use of stochastic rounding [5]. Figure 1 shows an example with a BNN version of LeNet-5 [6], where weights of the network are represented by Gaussian distributions. The ambiguous digit is classified as a ‘5’ and ‘3’ with probabilities of 80% and 20%, respectively. However, these uncertainty estimates come at great computational cost, as multiple forward inference passes are required to generate the necessary posterior distributions. As such, BNNs require not only efficient, high-performance multiply-accumulation (MAC), but an efficient Gaussian Random Number Generator (GRNG) with high-quality statistics as well.

A high-performance clock generator with extremely low jitter, area, and power consumption is the key building block in the emerging Internet of Things (IoT) to connect billions of devices. Recently, digital phase-locked loops (DPLL) [1,2] have been developed to eliminate the bulky loop filter (LF) in type-II charge-pump PLLs. However, they suffer from quantization noise and spurs, requiring complex calibration techniques. Therefore, type-I reference-sampling PLLs are gaining popularity [3, 4] to achieve wider bandwidths in smaller areas. A passive sampling phase detector (SPD) has a much lower noise contribution than a charge pump. But, a fractional-N implementation requires a digital-to-time converter (DTC) to align the input clocks of the SPD for spur mitigation [3]. Precise gain and nonlinearity calibrations are needed as the DTC delay can vary significantly with process-voltage-temperature (PVT) variations. This increases the complexity and loop convergence time, which are not preferable for IoT applications. A capacitive digital-to-analog-converter (CDAC)-based approach proposed in [4] relies on an accurate voltage reference provided externally, which also requires a calibration across PVT in practical implementations. This work presents a voltage-interpolation (VI) technique based on the capacitor charge sharing in a type-I sampling PLL to achieve the fractional-N operation and, therefore, eliminate a DTC or voltage reference and the associated complex calibration logic, providing fast phase locking. Furthermore, noise is minimized using a passive switch-capacitor-based VI (SC-VI), and the fractional frequency-synthesis resolution is enhanced utilizing a AZ-VI. Moreover, for edge-compute platforms, fast shutdown and restart of the clocking subsystem are necessary for efficient power management by transitioning among different power states. To enable such a requirement, the PLL is reconfigured to inject energy into the crystal for quick startup. Prior energy injection techniques in crystal oscillators for fast startup [5] used a dedicated ring voltage-controlled oscillator (VCO), which exhibited startup time uncertainty due to high jitter and frequency drift across PVT, requiring an additional frequency calibration step. In contrast, reusing the LC VCO inside a PLL that follows the crystal oscillator to perform frequency synthesis introduces less noise and frequency drift for robust startup while eliminating the VCO frequency calibration step. In addition, the chirp mechanism, which is similar to [5], sets the VCO frequency very close to the desired steady-state value, providing faster PLL locking.