Artificial intelligence (AI), once a mere figment of science fiction, has now entrenched itself deeply into our lives, reshaping everything from adjusting the tone of your email to assisting scientists analyzing deep space images captured by the James Webb space telescope. However, beneath the glorious appearance of the rapid development of AI technology, increasingly serious environmental problems are gradually emerging. To train and operate AI systems, power demand from data centers has skyrocketed, having tripled in just five years and being expected to triple again by 2030 [1]. This staggering increase starkly contrasts with less than 3% of annual global electricity production growth witnessed over the past 40 years, far outpaced by AI's ballooning energy needs [2], as shown in Figure 1 left. If we continue down this path relying on traditional processors, the growth of large language models (LLMs) may soon reach an unsustainable ceiling. This urgency is amplified by the reality that early efficiency gains in AI hardware are plateauing. Data centers nowadays principally utilize GPUs for both training and inferences. While GPU manufacturers often highlight improvements in efficiency—claiming a 40,000x improvement over the past decade—these numbers obscure several underlying concerns [3]. Upon scrutinizing the sources of the improvement, it becomes evident that sustaining such a pace of progress will be fraught with challenges. The main drivers of efficiency enhancement stem from circuit/architecture innovations, semiconductor process advancements, and data format optimizations.

Most analog compute-in-memory (ACiM) works only focus on the multiple-accumulate (MAC) operation while neglecting the activation function (AF) in the digital domain. The frequent data conversion greatly reduces the benefits obtained by analog computing. This letter proposes an efficient 8-bit in-memory MAC with hybrid capacitor ladders. Then, a sparsity-aware R-2R DAC and an embedded SAR-ADC that reuses the capacitor ladders in the MAC are introduced to reduce the conversion overhead. Two on-chip AF schemes are included to further improve efficiency. Finally, differential signal path offers first-order PVT cancellation that improves computing accuracy and reduces the need for calibration.

Frequent data conversion in analog compute-in-memory (ACiM) reduces the benefits obtained by analog computing. This paper proposes an efficient signed 8b multiple-accumulate (MAC) unit with hybrid differential capacitor ladders. Then a sparsity-aware DAC and an embedded SAR-ADC are introduced to lower the data conversion overhead. Finally, two activation functions (AFs) are included to further improve efficiency: 1) ReLU is realized by SAR-ADC LSB skipping; 2) tanh is built with analog buffers to bypass data converters.

Micro-RNAs (miRNAs) and circular-RNAs (circRNAs) are attracting attention as biomarkers for cancer diagnosis due to their distinct biological characteristics. MiRNAs, known for their critical role in gene regulation and tissue specificity, face challenges in detection due to their small size and low abundance in clinical samples. CircRNAs, on the other hand, offer advantages in stability based on their circular structure and are emerging as robust biomarkers. Traditional detection methods have limitations in sensitivity and specificity. Recent developments in isothermal amplification methods promise improved detection capabilities. This review focuses on the innovative primer/probe designs, which enhanced the efficiency of miRNA and circRNA detection in real samples.

Bayesian neural networks (BNNs) have been proposed to address the problems of overfitting and overconfident decision making, common in conventional neural networks (NNs), due to their ability to model and express uncertainty in their predictions. However, BNNs require multiple inference passes to produce the necessary posterior distributions used to generate these highly desirable uncertainty estimates. As such, BNNs require not only an efficient, high-performance multiply-accumulation (MAC) operation but also an efficient Gaussian random number generator (GRNG) with high-quality statistics. In this article, an NN accelerator chip, leveraging a multi-bit analog compute-in-memory (CiM) static random-access memory (SRAM) macro, with a tightly coupled and highly efficient GRNG scheme, is presented in the Intel 22FFL process. The CiM macro achieves a peak energy efficiency of 32.2 TOP/sW, with 8-bit precision, while ensuring accurate on-chip matrix-vector multiplications (MVMs) with a computation error less than 0.5%. The variable precision GRNG achieves a peak throughput of 7.31 GSamp/s for an energy efficiency of $\sim $ 1 TSamp/J. Overall, our proposed system achieves a peak energy efficiency of 1170 GOP/s/W, a 35–133 $\times $ improvement over the state-of-the-art BNN accelerators, with 98.14% accuracy for the MNIST dataset.

Compute-in-memory (CiM) is one promising solution to address the memory bottleneck existing in traditional computing architectures. However, the tradeoff between energy efficiency and computing precision plagues most CiM implementations, and the low precision imposes a major limitation on CiM’s ability to support practical computational workloads. In this article, a static random access memory (SRAM)-based analog CiM macro is presented with the Intel 22FFL process. By introducing a 1-to-2 ratioed capacitor ladder (C-2C)-based charge domain computing scheme, the proposed CiM prototype chip demonstrates a maximum of 2k multiply-accumulate (MAC) operations in one clock cycle and achieves 32.2-TOPS/W peak power efficiency with 8-bit precision in both input activation and weight while ensuring accurate on-chip matrix–vector multiplications (MVMs) with a computation error less than 0.5%. A 4.0-TOPS/mm2 peak area efficiency is attained by adopting a local weight multiplexing scheme with a 9T SRAM cell, which improves the memory density and reduces the need to refresh the weight stored in the SRAM array. A variety of analog impairment factors, including parasitics, mismatch, and noise, were analyzed to guarantee a sufficiently high multibit linearity. The proposed passive analog computing mechanism ensures the computation accuracy over process–voltage–temperature (PVT), with the measured MVM error deviation of less than 1% over PVT variations.

the resources required by artificial intelligence increase unsustainably, an analog design provides an energy-efficient alternative to digital computer chips — and one that is ideally suited to neural-network computations.

This paper presents an SRAM-based analog Compute-in-Memory (CiM) macro in 22 nm CMOS process. By introducing a C-2C capacitor ladder-based charge domain computing scheme, the CiM prototype chip demonstrates 2k multiply-accumulation (MAC) operations in one clock cycle and achieves 32.2 TOPS/W peak energy efficiency and 4.0 TOPS/mm2 peak area efficiency with 8-bit precision in both input activation and weight. A variety of analog impairment factors were analyzed during the testchip implementation to ensure sufficiently high multibit linearity.

In recent years, Neural Networks (NNs) have achieved tremendous success in a variety of fields, such as computer vision, natural language processing, speech recognition, autonomous driving, and healthcare [1] –[4]. However, conventional NNs rely heavily on large, labeled training datasets, which can lead to overfitting and overconfident decision making (especially when faced with unfamiliar, out-of-distribution inputs) [1] –[4]. Unlike conventional NNs, the weights of Bayesian Neural Network (BNNs) are represented by probability distributions, providing a mathematical framework to quantify the uncertainties in a model’s final prediction [3]. These uncertainty estimates allow BNNs to mitigate overfitting issues, enable training with smaller datasets, and help increase overall model accuracy through the implicit use of stochastic rounding [5]. Figure 1 shows an example with a BNN version of LeNet-5 [6], where weights of the network are represented by Gaussian distributions. The ambiguous digit is classified as a ‘5’ and ‘3’ with probabilities of 80% and 20%, respectively. However, these uncertainty estimates come at great computational cost, as multiple forward inference passes are required to generate the necessary posterior distributions. As such, BNNs require not only efficient, high-performance multiply-accumulation (MAC), but an efficient Gaussian Random Number Generator (GRNG) with high-quality statistics as well.

Recent advancements in performance, logic density, and power consumption of Field-Programmable Gate Arrays (FPGAs) have made them attractive for their widespread adoption into automotive, aircraft, space, military, and other safety-critical applications, in both embedded systems and cloud computing platforms. Every year, though, it becomes harder and harder to benefit from such advances in technology scaling due to smaller voltage margins, more aggressive clocking schemes, and greater device variability. FPGAs are often expected to last years or even decades in a variety of different environments before replacement. In some applications, they can be susceptible to soft and transient errors due to Single Event Upsets (SEUs), environment, and aging related effects. In this paper, we propose a simplified modular arithmetic technique based upon the concept of the digital root (DR) to monitor soft and transient errors, with low area overhead and high rates of detectability. The technique can be easily implemented at the register-transfer level (RTL) with no need to modify the underlying hardware of the FPGA. In one experiment, after dropping the supply voltage well below recommended design margins, we show in situ measurements on the instantaneous error rate in an Intel Arria 10 GX FPGA, which can be leveraged to optimize the power-performance trade-off of already deployed designs. We demonstrate this tradeoff, using an inherently error tolerant low-density parity-check (LDPC) decoder block, by either increasing the system clock beyond its synthesized target to achieve a 50% improvement in throughput, or by lowering the FPGA's supply voltage below synthesized design margins for a 65% reduction in power.

Integrated circuits, especially analog circuits, are highly sensitive to process, voltage, and temperature (PVT) variations. The information processed by analog circuits is often embedded in the amplitude of the waveforms, which requires circuits with high precision and high linearity. On the other hand, analog signal processing in time domain, such as (TDCs) and digital to-time converters (DTCs), was not widely adopted until the late 1990s when semiconductor technology advanced to the sub-micrometer region.

This article presents a direct RF-to-digital converter (RDC) for polar receivers, in which the amplitude information of the received signal is detected by a reconfigurable analog-to-digital converter (ADC) and its phase is digitized using a time-to-digital converter (TDC). The RDC prototype also includes a multi-phase reference generator and an ADC sampling position adjustment unit realizing the sub-sampling technique. Unlike conventional direct-RF sampling receivers, the proposed RDC samples the input RF signal at the baseband rate. The RDC is capable of digitizing a variety of modulation waveforms, such as quadrature amplitude modulation (QAM), phase shift keying (PSK), and amplitude phase shift keying (APSK). When comparing QAM to APSK, the later has advantages of relaxed system requirements on phase noise and linearity. The proposed direct RF-to-digital polar converter IC achieves a maximum data rate of 1.94 GB/s with a 1024-APSK modulation at a carrier frequency of 6 GHz, while consumes only 3.8 mW power under 1.1 V supply.

This paper presents a direct RF-to-digital converter (RDC) for polar RX. It consists of a pair of TDCs, an ADC, and a precise sampling position control system. Unlike conventional direct-RF sampling receivers, the RDC samples the input RF signal at baseband rate. It is capable of directly digitizing the phase and amplitude of the received modulated RF signals. It is compatible with a variety of modulations and has advantages of relaxed system requirements on phase noise and linearity when APSK is used. The RDC achieves a max rate of 1.94 GB/s with 1024-APSK at a carrier of 6 GHz, consuming only 3.8mW.

This paper presents the design of a fully self-timed 8-bit 80-Ms/s single-core SAR ADC with interleaved comparators and a high order compensated opamp-less bandgap reference. A 3/2 interleaving algorithm was designed for better SFDR performance, where two of the three comparators are orderly chosen for interleaving in each conversion while offset calibration is applied to the idle comparator. Asynchronized SAR logic with a DAC settling timer is designed for fully self-timing of the ADC. The ADC was designed with a PVT stabilized on-chip reference source which promises a stable reference for the ADC at extreme temperature environments such as aerospace exploration or quantum computing. Technique for compensating the temperature coefficient (TC) of a bandgap reference (BGR) using temperature characteristics of transistor's current gain β is proposed. Measured results show 42.8dB SNDR, 56.8 dB SFDR and -53.3dBc THD for the proposed SAR ADC, drawing 1.07mW from a 1.1v supply. Measured average TC of the HBT proposed BGR is 23ppm/°C and 39 ppm/°C over the commercial (0~70°C) and space (-260~125°C) temperature ranges, respectively. The BGR reaches PSRR of -50dB at 1MHz, and -38dB at 1GHz. The entire chip was implemented on 0.13um 8HP SiGe process with an active area of 0.2952 mm 2 .

This brief presents a technique for compensating the temperature coefficient (TC) of a bandgap reference (BGR) using temperature characteristics of transistor's current gain e̱ṯa̱. As a comparison, three BGR circuits built with Si BJTs and SiGe HBTs are implemented to demonstrate the proposed TC curvature compensation technique. Measured average TC of the HBT proposed BGR is 23ppm/ C and 39 ppm/ C over the commercial (0 70 C) and space (-260 125 C) temperature ranges, respectively. With the proposed PSRR improvement technique, the BGR reaches PSRR of -50dB at 1MHz, and -38dB at 1GHz, respectively.

A CMOS digital-bits-in/-out Terahertz (THz) nano-radio with 0.57mm 2 chip area is presented in this paper. The THz operation and bidirectional transmitter/receiver (TX/RX) architecture lead to radio ultra-miniaturization for Internet-of-Things (IoT) and field-deployable sensor applications. The bidirectional THz radio is configured as a harmonic oscillator in the TX mode or as a super-harmonic super-regenerative RX in the RX mode. The TX harmonic oscillator is directly modulated by On-Off Keying (OOK) data for bits-to-THz transmitting, while an on-chip time-to-digital converter (TDC) with 25ps timing resolution measures RX oscillation start-up time for direct THz-to-bits receiving. The radio peak DC power is optimized based on link distance and data rate. It supports maximum 4.4Mb/s OOK over 50cm at 49.3mW peak DC power and 1Mb/s OOK over 17cm at 18.7mW peak DC power without using any Silicon lens.

This paper presents an 8-bit 1.25-ps resolution reconfigurable Vernier time-to-digital converter (TDC) with a 2-D spiral comparator array and Delta Sigma modulators for linearization. The proposed spiral 2-D comparator array improves both linearity and detection range of the TDC. The quantization errors introduced by digitally tuning delay cells are minimized by using a 2nd-order AI modulator. The folding point errors commonly seen in 2-D comparator arrays are randomized by using a reconfigurable comparator array controlled by the output of a 2nd-order Delta Sigma modulator. The prototype TDC fabricated in a 45-nm silicon on insulator technology consumes 70- to 690-mu W power under a 1-V supply at 80-MHz conversion rate. The measured maximum differential nonlinearity/integral nonlinearity across its detectable range are 135/1.03 ps without the linearization techniques and 031/0.4 ps with the proposed linearization techniques, respectively.

This paper presents an analytical model on quadrature VCO (QVCO) phase noise performance as well as a wide-tuning triple band QVCO RFIC design. The phase noise model demonstrates the advantages of applying phase shift to quadrature coupling for QVCO phase noise reduction and bi-model oscillation elimination. As an example, we present a wide-tuning and low noise QVCO RFIC that contains a bottom-series QVCO with bipolar transistors for oscillation and NMOS transistors for coupling. The low-band and middle-band signals are generated from the QVCO outputs and its 2nd harmonics, while the high-band signal is obtained by frequency mixing. The tuning-range enhancement technique enables the triple-band frequency generation in the range from 1.4GHz to 8.7GHz without penalizing oscillator's phase noise. The proposed wide-band frequency generation RFIC is implemented in a 0.18 {\mu}m SiGe BiCMOS technology with 0.6mm2 area. The measured phase-noise is -125.2, -119.5 and -108.8dBc/Hz at 1 MHz offset for the three bands, respectively.

This work presents an 8-bit 1.25ps resolution Vernier TDC with 2D reconfigurable spiral arbiter array and ΔΣ linearization for ADPLL. The 2D spiral arbiter array improves both linearity and detection range. The quantization errors introduced by delay cells and 2D arbiter array folding points are minimized using a reconfigurable arbiter array with 2 nd order ΔΣ modulators. The prototype in a 45nm CMOS technology consumes 0.3mW power under a 1V power supply with 80MHz conversion rate. The measured maximum DNL/INL are 0.31/0.4 ps with ΔΣ linearization and 1.35/1.03 ps without ΔΣ linearization, respectively.