This work reports on the epitaxial growth of crystalline high- k oxide Gd 2 O 3 on Si (111) by Molecular Beam Epitaxy (MBE) for CMOS gate application. Epitaxial Gd 2 O 3 films of different thicknesses have been deposited on Si (111) between 650°C~750°C. Electrical characterizations reveal that the sample grown at the optimal temperature (700°C) presents an equivalent oxide thickness (EOT) of 0.73nm with a leakage current density of 3.6×10 -2 A/cm 2 at |V g- V FB |=1V. Different Post deposition Annealing (PDA) treatments have been performed for the samples grown under optimal condition. The Gd 2 O 3 films exhibit good stability and the PDA processes can effectively reduce the defect density in the oxide layer, which results in higher performances of the Gd 2 O 3 /Si (111) capacitor.

This work reports on the development of thin amorphous LaAlO"3 (LAO) layers on Si(001) for their integration as gate oxide in sub-22nm CMOS technologies. The crucial influence of the Si surface preparation is highlighted and an optimized surface preparation procedure is proposed. An unexpected interface reaction during Rapid Thermal Annealing is also evidenced, and an explanation attempt of the origin of this reaction, involving surface contaminants, is proposed.

In this paper, we investigate the causes for electron mobility reduction inside the conduction channel of nMOSFETs with TiN/HfO2/SiO2 gate stack. The use of such a high-k gate dielectric stack induces new interactions compared to conventional SiO2 gate oxide, modifying the electrons momentum during their transport along the channel. Experimental results, obtained by split-CV at different temperatures and charge pumping techniques, allow us to separate the contribution of each known interaction in the mobility degradation. Remote interactions are found to be the main phenomena at stake, specifically remote coulomb scattering, which modifies the screened potential seen by electrons in the channel. We finally discuss about the nature and the localization of such an interaction within the gate stack.

In this paper, an accurate capacitance extraction method, based on high frequency measurements (100MHz-1GHz), is used to study the carrier mobility in conventional nMOSFETs and metal/high-k gate stacked nMOSFETs. Simulations have been made to extract the main physical parameters. Effective carrier mobility is extracted, using a split CV methodology and a comparison is drawn between RF (radio frequency) and LF (low frequency) measurements for RF dedicated devices. Several problems encountered during high frequency measurements are also discussed. Finally, a method for using RF split CV with any kind of devices is proposed.

Spatial distributions of electrically active defects in dual-layer (SiO2∕HfO2) gate dielectric n-type metal oxide semiconductor transistors have been determined by charge pumping and 1∕f low-frequency noise measurements. Oxide trap concentration levels extracted from both techniques are in good agreement and appear one decade greater for HfO2 oxides compared to the reference SiO2 one. Moreover an increase in the trap concentration at the SiO2∕HfO2 is observed that could explain threshold voltage instabilities currently observed in HfO2 based transistors.

This article reports on the epitaxy of crystalline high κ oxide Gd2O3 layers on Si(111) for CMOS gate application. Epitaxial Gd2O3 thin films have been grown by Molecular Beam Epitaxy (MBE) on Si(111) substrates between 650 and 750°C. The structural and electrical properties were investigated depending on the growth temperature. The C–V measurements reveal that equivalent oxide thickness (EOT) equals 0.7nm for the sample deposited at the optimal temperature of 700°C with a relatively low leakage current of 3.6×10−2A/cm2 at |Vg−VFB|=1V.

Amorphous LaAlO3 high-κ oxides were grown in a molecular beam epitaxy reactor on p-Si(001) employing a thin γ-Al2O3 epitaxial layer as buffer. Interfaces are free of SiO2 and silicates and remain abrupt even after high temperature annealing as demonstrated by x-ray photoelectron spectroscopy. Electrical measurements performed on as-deposited samples reveal dielectric constant values close to the bulk ones, small equivalent oxide thickness, and low interface state densities. Some negative charges are present leading to a flatband voltage shift. Postdeposition annealing can correct this effect.

The properties of SrTiO3 thin films, grown by liquid injection metal organic chemical vapor deposition on Si/SiO2, using a mixture of precursors, have been investigated at the nanoscale using an Atomic Force Microscope in the so-called Conductive Atomic Force Microscopy mode. Maps of the leakage currents with a nanometric resolution have been obtained on films elaborated at different temperatures and stoichiometries in order to discriminate the role of each parameter on the onset of leakage currents in the resulting layers. It appears that the higher the deposition temperature, the higher the leakage currents of the films. The mapping with a nanometric precision allows to show a heterogeneous behaviour of the surface with leaky grains and insulating boundaries. The study of films elaborated at the same temperature with different compositions supports the assumption that the leakage currents on Ti-rich layers are far higher than on Sr-rich layers.

A specific time-resolved dynamic current measurement procedure is used to characterize high-field electron tunnel injection to the drain of EEPROMs. This allows the direct observation of a transient regime eventually occurring in the case of moderately doped drain. Another peculiarity is also evidenced, namely a stationary regime where measured current is far higher than anticipated by simulation. This is attributed to a non-equilibrium charge versus band-bending in the drain which is controlled by electron–hole pairs subsequent to impact ionization of electrons tunnelling from the gate.

From quantum simulations of both capacitance and current measurements, the main physical parameters (dielectric thickness and permittivity, doping levels) of hafnium based (HfSiOx and HfO2) gate oxide capacitors have been extracted. Three kinds of gates (n+-polysilicon, totally silicided (TOSI) NiSi and metal TiN gates) have been studied. In the case of thick (EOT between 11.1 and 12.3nm) HfSiOx gate oxides or thin (EOT inferior to 2nm) HfO2 stacks with n+-polysilicon or TiN gates, a good agreement between simulations and experimental data is obtained. Electron tunneling currents are prevalent in these stacks except for the specific case of TiN/HfO2 stacks in p-substrate accumulation mode. In this case, electron and hole tunneling transparencies become of the same order of magnitude. Hole transport contribution can no more be neglected and should be taken into account in simulations.

High-field Fowler-Nordheim electron injection to the drain of EEPROM's is studied using a specific time-resolved measurement technique. A transient injection regime is observed only in the case of moderately doped drain, but a nonequilibrium stationary injection regime is always evidenced, resulting, for a given temperature, in a current higher than expected for thermal equilibrium conditions. The magnitude of the phenomenon is shown to decrease with temperature and doping level. As a consequence, the memory cell programming window change with temperature, which is controlled by the total FN characteristics voltage shifts with temperature, should depend on drain doping and programming current.

Stress induced leakage currents (SILC) remain one of the main reliability problems preventing further SiO2 tunnel oxide thickness reduction in floating thin oxide (FLOTOX) memory devices. In this work, we present ultra-low level SILC current-voltage (I-V) measurements performed by using the floating gate technique on 7-8 nm thick SiO2 tunnel oxides and low-level measurements performed by direct technique measurements. Experimental characteristics obtained by the indirect measurement technique reached current levels as low as 2 x 10(-17) A. They exhibit new phenomena such as negative differential resistance behavior and current threshold voltages. A physical one-step tunneling model (A-mode), taking into account the influence of defects located in the bulk SiO2 is proposed. Both spatial and energetical defect profiles are extracted from experimental data. We show that the new phenomena experimentally observed can be interpreted as a one step trap-assisted tunneling mechanism via defects located near the middle oxide, even for highly stressed components. (C) 2007 Elsevier B.V. All rights reserved.

In this study, the critical parameters relevant to endurance of EEPROM memory cells are theoretically determined from cells geometrical design and programming pulses temporal shape. A new experimental technique is then proposed to realize realistic current pulsed stresses on dedicated large area cell test structures. The influence of the different relevant pulses parameters is finally experimentally studied and discussed.

This paper presents two power devices architectures designed for 20V and 10V power management switching applications, respectively, the separated drain MOSFET one and the drain extension MOSFET. Global losses are evaluated through R/sub on/*C/sub gg/ figure of merit. Electrical results bring forward the dummy gated separated drain MOSFET for 20V application and confirm the drain extension MOSFET as a serious competitor for 10V applications.

A novel dynamic gate capacitance characterization technique is proposed to evaluate switching losses in power devices. Dynamic gate capacitance is obtained by measuring the gate displacement current due to the application of a controlled gate voltage pulse, closely matching real operation conditions of power switches. Several architectures for 20-V MOSFET transistors, integrated in a low-cost power management 0.13-/spl mu/m CMOS technology, are studied. Experimental results are compared to a specific small-signal model for switching transition gate capacitance.

Switching performances of low-cost 20V drift-MOSFETs and diffused-MOSFETs power devices are compared. Thanks to a new dynamic gate capacitance measurement protocol, the average gate capacitance responsible for power losses during fast switching transitions is estimated and the Miller effect contribution is quantified. Optimized drift-MOSFETs with reduced gate length and gate to drain overlap present comparable and even better performances than diffused-MOSFETs. Moreover they present the lowest process over-cost, making them excellent and very competitive candidates for low-cost portable power management applications

The purpose of this work is to investigate the dynamic behaviour of Fowler–Nordeim injection through EEPROM tunnel oxides, in conditions representative of the standard device operation. An experimental procedure based on the acquisition of current transients induced by trapezoidal-shape short voltage pulses is presented. It is then used to evidence a rapid positive charging and to determine some of its properties. Implications regarding the device behaviour and modelling are finally discussed.

This paper is devoted to the understanding of Electrically Erasable Programmable Read Only Memory (EEPROM) programming window (PW) changes with operating temperature. First a theoretical analysis is carried out, and two main contributions to the PW change are identified: change of the sense transistor characteristics and variation of the FN (Fowler–Nordheim) injection mechanism. An experimental study is then conducted on samples with various size (0.8 and 19360μm2) and coupling coefficients (0.45, 0.62 and 0.71), for temperatures in the range 25–200°C. Whereas the results concerning the erased mode are reproducible and quantitatively explained by the model, data relative to the written state of real size cells features an irreproducible behavior which was not elucidated.

We present a detailed analysis of electrically active gate oxide defects on damascene CMOS devices with a HfO/sub 2/ gate dielectric and a TiN/W gate electrode. The interface state density (D/sub it/) and the trapped oxide charge (N/sub it/) are determined by 2 and 3-level charge pumping analysis on high-quality nMOS and pMOS transistors. Furthermore, we discuss the influence of the gate stack defects on the carrier mobility in the channel and correlate the reduction of the gate oxide defect density to a mobility improvement for both electrons and holes.

This work deals with the programming window closure observed in electrically erasable programmable read only memories as the number of write/erase cycles increases. This aging phenomenon is attributed to the build-up of oxide charge in the tunnel area. Capacitance–voltage and current–voltage measurements on 8.5 nm thick oxide MOS capacitors performed after constant current Fowler–Nordheim (FN) stresses showed interface states generation at both the anode and the cathode. A linear build-up of ‘slow’ states with the total injected charge was also observed at the cathode. Bulk oxide trapped charge and normalized centroid were deduced from the DiMaria technique. The bulk oxide charge build-up after FN stress is shown to follow a power law as a function of injected electron density over several decades. The charging kinetics have been explained by two components: trapping by native and generated traps. We have determined the different trap parameters (densities, capture cross-sections, generation rates and locations). By varying the stress current (polarity and density), we have noticed that the change in generated trap parameters is linear with the stress bias. We take finally a particular interest in the cumulating effects of different stresses. To our knowledge, such a complete study is absent from the literature and has to be done to predict the charge trapping kinetics due to non-constant stress which occur during memory write and erase operations.