General Matrix–Matrix Multiplication (GEMM) serves as a fundamental computation kernel in modern AI and high-performance workloads. However, conventional multi-core AI processors fail to fully exploit the inherent data reuse in large GEMM operations, leading to excessive bandwidth demand and inefficient utilization of on-chip SRAM. This work proposes a dual-ring interconnect that fully leverages the data reuse and locality inherent in GEMM computation. The proposed architecture enables direct, local data exchange among adjacent cores, eliminating redundant copies and significantly reducing both memory bandwidth requirements and on-chip SRAM occupation. Furthermore, the dual-ring design is lightweight and area-efficient, relying solely on local and direct connections to achieve high performance with minimal hardware overhead. Evaluation across different GEMM scales demonstrates that the proposed dual-ring interconnect with cluster 4x4 achieves a 3.61×–4.2× reduction in L2 bandwidth consumption and a 3.2× saving in SRAM usage, while incurring only a 0.19% overhead in silicon area.

Abstract Epilepsy is a debilitating condition characterized by recurrent seizures and associated mortality risks. Developing accurate and computationally efficient electronic systems for epilepsy prediction remains a critical yet unresolved challenge. Conventional approaches directly employ time-frequency transformations to extract features for neural networks, resulting in significant redundancy and high computational costs. This paper proposes a systematic two-stage training framework that utilizes attention mechanisms for input optimization, aiming to achieve a lightweight neural network to classify epilepsy stages. During the first stage of the proposed framework, the base model incorporating a convolutional block attention module is trained to generate a quantitative spatial importance ranking, where the mel-frequency cepstral coefficients (MFCC) are employed to achieve superior distinguishing performance. Within the second stage, the ranking results will serve as prior knowledge to construct a lightweight network model, which is architecturally adjusted to process only the most informative subset within the time-frequency map. With the proposed two-stage training framework, the neural network demonstrates a highly favorable trade-off between efficiency and performance for the epilepsy prediction task on the CHB-MIT dataset. By selecting the five most significant spatial rows in the MFCC feature map identified in the first stage, the parameter count of the network is reduced from 116k – 18.3k (with a reduction of 84.2%), with a computational load of only 247.59 kMACs. Furthermore, this optimization is achieved while maintaining an accuracy of 97.43%, compared to the baseline model’s accuracy of 98.91%.

With the deployment of deep neural networks to edge devices, low-bit (e.g., 4-bit) quantization has become a key technology for reducing computational and storage overhead. However, at low bit-widths, conventional one-dimensional activation functions face the challenge of numerical diversity loss, where a large number of features are merged into a limited number of quantization levels, resulting in significant information loss. For 4-bit quantized neural networks, this paper proposes Bivariate Lookup Table Activation, based on adaptive channel grouping. This method utilizes the channel locality of memory layout to design a channel cyclic shift operator without additional copies. Crucially, it introduces a correlation-based static reordering mechanism. By employing a spatial flattening strategy and a greedy sequence construction algorithm, the method maps semantically correlated channels to physically adjacent positions offline, thereby maximizing the validity of context information without increasing inference overhead. Coupled with a differentiable training technique based on bilinear interpolation it achieves the joint optimization of LUT parameters and network weights, overcoming the context-independent limitation of traditional one-dimensional activation functions. By introducing features from physically adjacent channels as context inputs, this paper constructs a two-dimensional mapping relationship that expands the theoretical input combinations from 16 to 256 without increasing the input bit-width, thereby enhancing the diversity of output feature representation. Experimental results demonstrate that this paper achieves $\mathbf{4}$-bit quantization performance of $\mathbf{6 9. 1 \%}$ (Top-1 accuracy) on ResNet-18 (ImageNet) and 77.5% ($\text{mAP}_{0.5}$) on YOLOv5s (Pascal VOC), respectively, outperforming existing methods such as LSQ. Furthermore, it adds a negligible storage overhead of only 128 bytes per layer, effectively balancing accuracy and efficiency in edge inference.

With the scale up of neural network (NN) accelerators, it is crucial to maintain a high utilization rate by processing different layers of NNs in pipeline. Previous works exclusively adopt dynamic networks on chip (NoCs) to transmit data between data-dependent layers, which are not optimal for NN inter-layer acceleration. Considering the dataflow between the NN layers is priorly known, we designed a statically scheduled network to transmit data between data-independent layers in NNs. The statically scheduled network can be configured to support many-to-many communication between layers, which is the essential traffic pattern in inter-layer acceleration. We also proposed a gather-scatter pathfinding algorithm to avoid deadlock and developed a compiler to automate the mapping from the data dependency in neural networks to the configuration of the statically scheduled network. Evaluation demonstrates the statically scheduled network costs 7.8x less area, delivers 2.54 & times; to 3.35 & times; higher throughput, and achieves 5.6x to 9.9x power saving for inter-layer acceleration, compared to previous works.

Abstract Neuromorphic vision systems based on memristors offer an energy-efficient approach to artificial vision, yet traditional pixel(s)-to-one-memristor architectures remain inefficient in dynamic image processing due to limited temporary storage. Here, inspired by human visual working memory, we propose a one-pixel-multiple-memristor (1PnR) architecture with a rolling exposure strategy for fast sequential image acquisition. Furthermore, a data-in-situ computing network for efficient image processing is developed. With network weights mapped to voltage vectors and applied to the image storage memristor array, direct computation is enabled where the image is stored, and the energy-intensive data transmission is eliminated. A hardware prototype of the 1PnR architecture achieved 95.7% recognition accuracy on the Weizmann human action flow dataset. Compared to CMOS-based systems, this architecture is estimated to have a 2000× reduction in latency for image sensing and storage, and a 160× reduction in energy consumption image processing, demonstrating significant potential for future neuromorphic visual systems.

Vision transformer (ViT)-based models have achieved state-of-the-art accuracy in many computer vision tasks, but their attention mechanism is more computation and communication intensive than convolutional neural networks (CNNs). To adapt ViT-based models for resource-constrained edge computing platforms, techniques, such as network sparsity and convolution-attention combination, have been proposed to reduce processing costs without compromising accuracy. Therefore, specific hardware designs able to handle sparsity in both convolution and attention operations are required to accelerate the processing speed. In view of this, this work proposes OPASCA, an accelerator featuring a unified hardware architecture that supports irregular activation and weight sparsity in both operations. Specifically, this target is achieved with the following contributions: 1) we employ outer product dataflow to efficiently handle sparse weights and input neurons, supporting both convolution and attention computing with minimal hardware overhead; 2) we design a hierarchical butterfly network to route the output neurons to the accumulation buffers, minimizing the conflicts among outer product results and reducing the hardware overhead of accumulation banks; and 3) we propose a novel encoding scheme that achieves more compact sparse inputs and enhances multiplier utilization. Evaluations on VGG-16, ViT, BoTNet, and Conformer models show that OPASCA outperforms state-of-the-art accelerators by 1.60x-2.08x on sparse convolution tasks and by 1.18x-1.70x on sparse attention tasks in term of performance. It also reduces DRAM access to 19%-86% and energy consumption to 36%-92% of those of the counterpart designs.

Compute-in-Memory (CIM) and weight sparsity are two effective techniques to reduce data movement during Neural Network (NN) inference. However, they can hardly be employed in the same accelerator simultaneously because CIM requires structural compute patterns which are disrupted in sparse NNs. In this paper, we partially solve this issue by proposing a bit level weight reordering strategy which can realize compact mapping of sparse NN weight matrices onto Resistive Random Access Memory (RRAM) based NN Accelerators (RRAM-Acc). In specific, when weights are mapped to RRAM crossbars in a binary complement manner, we can observe that, which can also be mathematically proven, bit-level sparsity and similarity commonly exist in the crossbars. The bit reordering method treats bit sparsity as a special case of bit similarity, reserve only one column in a pair of columns that have identical bit values, and then map the compressed weight matrices into Operation Units (OU). The performance of our design is evaluated with typical NNs. Simulation results show a 61.24% average performance improvement and 1.51x-2.52x energy savings under different sparsity ratios, with only slight overhead compared to the state-of-the-art design.

Resistive Random Access Memory (RRAM) based Compute-in-Memory (CiM) has attracted extensive research for the capability to improve energy efficiency in Convolutional Neural Networks (CNNs) based image processing. However, existing solutions typically require image data to be converted from analog to digital for transmission between the sensor and the processor, and then converted back to analog for processing in the CiM macros, which substantially increases energy and area overhead. In fact, analog pixel signals can be directly modulated to pulse-width and then fed into the CiM macro for computation. Nevertheless, traditional Pulse-Width Modulation (PWM) suffers from exponential latency increase for high resolutions. To overcome this limitation, we propose a Segmented Voltage-to-Pulse-Width Converter (S-VPWC) circuit and validate its performance in the RRAM array. The circuit achieves a conversion latency of only 110 ns and a power consumption of 6.08 mW, with 8-bit resolution by dividing analog pixel signals into two segments for pulse-width generation and computation, while outputting 10-bit precision with an average accuracy of 90.59% in the CiM macro.

With the rise of compute-in-memory (CIM) accelerators, floating-point multiply-and-accumulate (FP-MAC) operations have gained extensive attention for their higher accuracy over integer MACs in neural networks. However, the hardware overhead caused by exponent comparison and mantissa alignment, along with the delay introduced by bit-serial input methods, remains a hinder to implement FP-MAC efficiently. In view of this, we propose Segmented Exponent Alignment (SEA) and Dynamic Wordline Activation (DWA) strategies. SEA exploits the observation that input exponents are often clustered around zero or within a narrow range. By segmenting the exponent space and aligning mantissas accordingly, SEA eliminates the need for maximum exponent detection and reduces input mantissa shifting, and thus reduces the processing latency. DWA further reduces latency and maintains accuracy by activating wordlines based on the exponent segments defined by SEA. Simulation results demonstrate that, when compared with conventional comparison tree based maximum exponent alignment method, our approach saves 63.8% power consumption, and achieves a 40.87% delay reduction on the VGG16-CIFAR10 benchmark.

Spiking Neural Networks (SNNs) possess excellent computational energy efficiency and biological credibility. Among them, Spiking Convolutional Neural Networks (SCNNs) have significantly improved performance, demonstrating promising applications in low-power and brain-like computing. To achieve hardware acceleration for SCNNs, we propose an efficient FPGA accelerator architecture with multi-structure compatibility. This architecture supports both traditional convolutional and residual topologies, and can be adapted to diverse requirements from small networks to complex networks. This architecture uses a clock-driven scheme to perform convolution and neuron updates based on the spike-encoded image at each timestep. Through hierarchical pipelining and channel parallelization strategies, the computation speed of SCNNs is increased. To address the issue of current accelerators only supporting simple network, this architecture combines configuration and scheduling methods, including grouped reuse computation and line-by-line multi-timestep computation to accelerate deep networks with lots of channels and large feature map sizes. Based on the proposed accelerator architecture, we evaluated two scales of networks, named small-scale LeNet and deep residual SCNN, for object detection. Experiments show that the proposed accelerator achieves a maximum recognition speed of 1, 605 frames/s at a 100 MHz clock for the LeNet network, consuming only 0.65 mJ per image. Furthermore, the accelerator, combined with the proposed configuration and scheduling methods, achieves acceleration for each residual module in the deep residual SCNN, reaching a processing speed of 2.59 times that of the CPU with a power consumption of only 16.77% of the CPU. This demonstrates that the proposed accelerator architecture can achieve higher energy efficiency, compatibility, and wider applicability.

Ferroelectric thin film transistors (FeTFTs) have attracted great attention for in-memory computing applications due to low power consumption and monolithic three-dimensional integration capability. Herein, we propose a planar integrated highly-reliable metal-ferroelectric-metal-insulator-semiconductor FeTFTs device, in which the weak erase issue is suppressed by implanting a floating gate, and the interface defects are reduced by simplifying the fabrication process. These lead to significant improvements in device performance, including large memory window (4.3 V), high conductance dynamic range (1400), high endurance (1012 ), and low variation (cycle-to-cycle: 2.5 %/device-to-device: 3.5 %). Moreover, we fabricated a 16 x 16 FeTFTs pseudo-crossbar array for in-memory computing and experimentally demonstrated full hardware implementation of multi-layer perceptron for the classification of four fundamental arithmetic operation symbols. This work provides a potential hardware solution for implementing a highly-efficient in-memory computing system based on highly-reliable FeTFTs array. (c) 2025 Published by Elsevier Ltd on behalf of The editorial office of Journal of Materials Science & Technology.

The one-transistor-one-resistor (1T1R) structure is a popular memristor crossbar structure. This structure can effectively suppress sneak current. However, the transistor suffered from excessive IR drop, resulting in uncontrolled energy consumption. To address this issue, we propose two optimal designs. The one is source-substrate shorting, which can improve the energy efficiency of the memristor by 5%-10%, but deep-well process may lead to extra chip layout area over 16 times. The other is to provide a negative voltage bias, which can significantly increase the power efficiency of the memristor at over 98% without increasing the layout area.

The non-maximal suppression (NMS) operator is widely utilized in the post-processing phase of target recognition neural networks. However, its high computation overhead and complex operational process, pose significant challenges to the efficiency of target recognition systems. Some works have been proposed to speed up NMS with FPGA but still cost too much latency and hardware resources. In view of this, we introduce a fast and resource friendly hardware NMS accelerator. Specifically, we first determine the most confidential category of each bounding box with a preprocessing unit, and then determine whether a box should be kept or not quickly by comparing its confidence and calculating the Intersection-Over-Union (IOU) with those of the previously stored boxes in parallel. Experimental results on the Xilinx VCK190 hardware platform reveal that, in comparison to the cutting-edge O3NMS accelerators, the proposed accelerator offers a substantial speedup of approximately 20% while utilizing 21.4% more LUTs and 81.5% less Flip Flops.

In Resistive Random Access Memory (RRAM) based compute-in-memory designs, the column current readout circuits still consume too much area and power overhead, even if plenty of methods have been proposed to optimize the circuits. To alleviate this problem, this paper presents a novel current readout circuit to sense multiply-and-accumulate (MAC) result of RRAM array. Specifically, the circuit first integrate the stabilized and proportionally mirrored MAC current on a small capacitor until it fires, then sample the integration time with a set of reference signals with different carefully designed delays, and finally code the sampled result into a digital value. The proposed readout circuit has fine stability due to simple and determined relationship among the inputs, the RRAM cells' states, and the MAC current. Meanwhile, the proposed design can achieve accurate MAC result readout at low resistance switching ratios, for it employs a current compensation circuit to remove background current caused by high resistance state RRAM cells. Our design is implemented using 28nm CMOS technology with a read latency of 2.8ns and an area occupation of 267 mu m(2)/channel, which is 12.5% and 89% less than state of the art design. Its power consumption, 0.092mW/channel, is also less than most counterpart designs.

Traffic Signs Recognition (TSR) is a key technology to implement Automatic Driving System (ADS) and Advanced Driver Assistant System (ADAS). Numerous efforts have been endeavored to improve the TSR accuracy and speed, and Convolution Neural Networks (CNN) are usually employed. However, most of the existing works require large network scale and thus suffer from the drawback of high computation and power consumption. To alleviate this issue, in this paper, we propose an SNN–CNN hybrid network with RRAM-implemented weights to improve the storage and computing efficiency of TSR. Specifically, we utilize SNN to quickly determine the superclass that a traffic sign belongs to. Then utilize CNNs to determine the subclass accurately, thus the complex TSR task is decomposed into multiple simple tasks. Finally, the network weights are binarized to alleviate the implementation of the hybrid network on RRAM-based accelerators, which have higher power efficiency than CMOS logic based ones. Experimental results indicate that, when compared with state of the art CNN method, the SNN–CNN hybrid network can achieve similar accuracy with less weight scale (−69.21%) and lower power consumption (−81.55%). Binarizing the hybrid network can further reduce the weights storage requirement by another 96.875% with only 1.518% accuracy loss. When the network weights are implemented with state of the art RRAM array (resistance variation is 5%), the proposed network can achieve a mean accuracy of 96.47% with 95% ∼ 97.5% confidence interval.

Spiking neural networks (SNN) have good computational energy efficiency and biological plausibility, and are promising for applications in low-power computing and brain-like computing. To achieve hardware acceleration of convolutional SNN (i.e., SCNN), we propose a configurable and extensible hardware architecture based on clock-driven design. In this architecture we use a strategy of output-channel-wise parallelism and hierarchical pipeline structure to speed up the computation. Aiming at retaining the performance when reducing the quantization bits, the adaptive channel-wise logarithmic quantization (ACLQ) method for SCNNs is proposed to ensure performance while significantly reducing the overhead on hardware resources such as on-chip memory. We configured and evaluated two sizes of LeNet networks model based on the proposed architecture in FPGA. Experiments show that our architecture achieved recognition accuracy of up to 99.26% on the MNIST dataset, while achieving a recognition speed of up to 1605 frames per second (FPS) at a 100MHz clock speed and consuming only 0.65mJ of energy to process each image. Using the proposed logarithmic quantization method, the weights’ bit width can be reduced to 3 bits with almost none of accuracy loss, which significantly reduces the on-chip resources and power consumption for weights storage.

The capability of multistate is critical for electronic synapses in neuromorphic computing. In this article, the multistate performance of the ferroelectric field-effect transistors (FeFETs) is investigated by inserting an Al $_{\mathbf {{2}}}~\text{O}_{\mathbf {{3}}}$ interlayer (IL) into Hf $_{\mathbf {{0}.{5}}}$ Zr0.5O2 film. The experimental results of characterization indicate that the grain sizes of the ferroelectric film can be effectively reduced by the Al $_{\mathbf {{2}}}~\text{O}_{\mathbf {{3}}}$ IL. Benefiting from the refined grain sizes, both the proposed ferroelectric capacitor and FeFET show excellent multistate performance and linearity. The benchmark with other emerging synaptic devices demonstrates that the back-end-of-line (BEOL) compatible FeFETs behave noticeable synaptic performances, such as 160 conductance states, low nonlinearity ( $\alpha _{\mathbf {p}}$ = −1.83 and $\alpha _{\mathbf {d}}$ = −1.39), high $G_{\mathbf {\textit {max}}}$ / $G_{\mathbf {\textit {min}}}$ (46.1), and low energy consumption (1.13 pJ).

In the design of memristive neuromorphic chip, the memristor array and its peripheral circuits need to be simulated to confirm the correctness of the circuit design. However, almost all existing memristor models are designed for a single device. When array simulation is carried out, a large amount of memristor models need to be instantiated to form an array, which usually consumes huge simulation time and memory. In order to improve the efficiency of circuit simulation, this paper proposes a memristor array simulation model for the design of memristive neuromorphic chips. The model simulates the largesize memristor array by combining the small-size memristor array with the lumped parasitic parameter models, which can accurately simulate the change of the resistance states of the operated devices and the action of the driving circuits, and also reduce the time and memory required for simulation. The experimental results show that, to simulate a 64×64 memristor array, this method can reduce simulation time and memory by 99.21% and 43.15% respectively, than those of instantiating all memristors.

In the design of memristive chips, memristor models are needed to evaluate the correctness of circuit design and simulation. Although numerous memristor models exist, they are usually too complicated to exhibit satisfactory simulation speed in large-scale arrays, or too concise to accurately reflect device characteristics. In this article, we propose a PieceWise linear (PWL) memristor model with well-balanced simulation speed and accuracy. The model has continuous state equation and contains only elementary operations to guarantee the simulation efficiency. The model parameters are derived with the minimum mean square error (MMSE) fitting method from the measured data. Simulation results illustrate that, with similar fitting accuracy, our model can reduces simulation time by 30% and memory usage by 11% than state-of-the-art models in a pure network with over $2\times 10^{4}$ memristors. The effectiveness of this model is also validated in a $32\times 64~1$ T1R array with weight update and signal processing operations.