In recent years, the use of highly parallelized and high-speed data links has exacerbated the problem of crosstalk coupling. Signals with high frequency components couple to and degrade the quality of signals in adjacent lines aggressively with reduced device dimensions. In this paper, we propose a methodology for characterizing multiple crosstalk jitter effects in the time domain using a single data capture without the use of any channel models. The method uses repetitive data patterns across different signal lines with coprime periods. Each signal with crosstalk effects is digitized using sub-Nyquist sampling, and after back-end digital signal processing, the original transmitted signal on each line is isolated from its crosstalk components. Mathematical analysis shows that only by using patterns with coprime lengths, unbiased crosstalk characterization is possible. Hardware measurements support the proposed test methodology.

Characterizing the spectrum of sparse wideband signals of high-speed devices efficiently and precisely is critical in high-speed test instrumentation design. Recently proposed sub-Nyquist rate sampling systems have the potential to significantly reduce the cost and complexity of sparse spectrum characterization; however, due to imperfections and variations in hardware design, numerous implementation and calibration issues have risen and need to be solved for robust and stable signal acquisition. In this paper, we propose a low-cost and low-complexity hardware architecture and associated asynchronous multi-rate sub-Nyquist rate sampling based algorithms for sparse spectrum characterization. The proposed scheme can be implemented with a single ADC or with multiple ADCs as in multi-channel or band-interleaved sensing architectures. Compared to other sub-Nyquist rate sampling methods, the proposed hardware scheme can achieve wideband sparse spectrum characterization with minimum cost and calibration effort. A hardware prototype built using off-the-shelf components is used to demonstrate the feasibility of the proposed approach.

Incoherent undersampling-based waveform acquisition provides a low-cost test setup for characterizing high-speed systems. A periodic waveform reconstruction using incoherent undersampling remaps time indices of samples using the modulus of the suspected period of the signal, effectively folding the signal into a time window equal to one period. The major cost and accuracy limitations of the reconstruction technique arise from estimation of the waveform period. Multiple cost functions have been proposed to estimate the period, including frequency domain metrics, which are computationally intensive. In this paper, we propose a new time domain zero-crossing (ZC)-based metric, where the metric gives the number of ZC in the reconstructed waveform for an assumed period of the waveform. The reconstruction technique is also extended to beyond the track-and-hold amplifier bandwidth using a novel test setup combining the incoherent undersampling with multichannel bandwidth interleaving.

Modern high speed communication systems often employ both analog and digital blocks. This poses a challenge for simulation of closed loop system dynamics in presence of non-idealities in any of the analog blocks. Due to the size and complexity of such systems it is not possible to do full system level simulation with circuit level models. The presence of digital control blocks makes it difficult to elevate block level observations to system level performance. A major challenge is the difficulty in estimating the error rate at the output of digital latches (continuous-time to discrete-time domain crossing boundaries) in the presence of noise and non-ideal analog input signals. Simplistic models used currently are often inadequate in capturing the long term effects of non ideal behavior at the block level. In this paper we propose a simulation framework to estimate latch transition probabilities in the response to distorted input and clock waveforms in presence of white noise. The evaluated transition probabilities can then be used to estimate system performance in an event driven Markov chain based model.

To meet the testing requirements of high speed components used in modern communication systems, in an efficient and cost effective manner, it is necessary to develop new device performance measurement techniques that are easily scalable to high frequencies. Traditional up/down conversion based transmitter testing architectures are sensitive to the linearity of the mixers and carrier phase noise in the receiver. Direct undersampling based test instrumentation can overcome the limitations imposed by mixers in up/down conversion. A major challenge in direct undersampling based test architecture is to achieve precise phase alignment between different components of the test setup. Such phase alignment of high frequency signals requires the use of expensive test instruments adding to the cost and complexity of the overall test system. To resolve this problem, an incoherent undersampling based test method is developed in this research that eliminates the need for precise phase synchronization between the RF test signal carrier, its amplitude-modulated envelope (generally necessary for measuring amplifier nonlinearity) and the reference sampling clock. A side-benefit, due to the use of signal undersampling, is that signal acquisition is achieved without the use of a Nyquist rate data converter. Multiple RF performance metrics are extracted without the use of a reference receiver. The accuracy of the proposed setup is compared against existing coherent sampling based test setups.

As communication data rates increase, wideband signals are being increasingly used to accommodate high rates of information transmission. Acquiring and characterizing the time domain waveform of such signals requires high measurement system sampling rate and wide input bandwidth and is thus, expensive. A key problem that drives up the cost of traditional bandwidth interleaved data acquisition systems is the need to synchronize the input signal (periodic) with the sampling clock as well as the oscillator inputs to all the mixers in the band interleaved architecture. This synchronization problem is complicated at multi-GHz frequencies and increases overall design cost. In this paper, we propose a low-cost band-interleaved architecture that uses: (a) incoherent undersampling to acquire the signal across the frequency bands of the band-interleaved system and (b) does not require any mutual synchronization between the input signal, the undersampling clocks and the mixing signals (local oscillators) of each frequency band in the band-interleaved system. The reconstruction is achieved through back-end spectrum analysis and use of signal processing algorithms that compensate for the lack of synchronization. The proposed technique is supported by hardware validation experiments.

Modern microprocessor pipelines experience timing uncertainties due to manufacturing process variations, thermal variations, supply voltage droop and data-dependent path delays. This leads to power and/or performance inefficiencies in current timing guard banding methods especially when pipeline stages are operating well under their critical path timing constraints due to the temporal characteristics of input data. In this paper, we propose a novel adaptive pipeline design that automatically adjusts to timing variations, thus reducing/eliminating the need for design guard banding. Each pipeline stage is equipped with an activity completion sensor that determines switching activity completion in the respective pipeline stage with a very high probability of correctness. The switching activity completion detection is used to trigger handoff of data from one pipeline stage to another. The pipeline is equipped with low overhead back-up error resilient circuits to handle incorrect (but infrequent) completion sensing and continue forward progress. Such a scheme enables time lending between pipeline stages, thus allowing correct pipeline computations at a lower voltage/higher clock frequency as compared to fully synchronous designs. Simulations and layout generated results from extracted net lists of pipelined arithmetic designs show 32.52% improvement in throughput at same supply voltage or 18% lesser power for the same throughput over conventional fully synchronous design incorporating worst-case safety margins.

Incoherent undersampling provides a low cost solution for wideband periodic waveform acquisition without the requirement for synchronization with the source clock. The bandwidth of a traditional incoherent undersampling based test setup is limited by the the bandwidth of the track and hold amplifier. In this work, a test setup is proposed combining incoherent undersampling and bandwidth interleaving to break the bandwidth barrier of the track and hold amplifier. The high frequency components of the signal waveform beyond the track and hold bandwidth are down converted using mixers and undersampled. While bandwidth interleaved frequency domain signal reconstruction techniques have been proposed before, this is the first time that fast time domain reconstruction techniques are used for periodic waveform reconstruction of wideband signals in the absence of any synchronization between the test signal and the tester oscillator/sampling clock over multiple frequency bands by choosing the local oscillator frequency to be a multiple of the sampling frequency. The periodic test signal waveform is acquired over multiple channels each covering only part of the total bandwidth of the signal. Feasibility of the proposed technique is shown through simulation and hardware results.

Measurement of the quality of tests run during high volume manufacturing of microprocessors is important to ensure desired outgoing product quality. For digital logic on die, such measurement is performed using techniques such as fast event-driven fault simulation using mature fault models such as stuck-at and transition faults. For analog modules on die, such test quality measurement is not performed in practice due to lack of (a) mature fault models to describe analog failures, and (b) automated, efficient and accurate fault simulation methods. This work is a first step towards our objective of establishing a practical methodology to measure analog test quality. We show promising results of a semi-automated fault simulation approach on analog modules of a high speed serial IO receiver that compares (a) two manufacturing tests in terms of their defect detection capability as measured by their fault coverages for gross and parametric faults, and, (b) the accuracy and performance of using models versus schematics for fault effect propagation.

Jitter measurement is an essential part for testing high speed digital I/O and clock distribution networks. Precise jitter characterization of signals at critical internal nodes provides valuable information for hardware fault diagnosis and next generation design. Recently, incoherent undersampling has been proposed as a low-cost solution for signal integrity characterization at high data rate. Incoherent undersampling drastically reduces the sampling rate compared to Nyquist rate sampling without relying on the availability of a data synchronous clock. In this paper, we propose a jitter decomposition and characterization method based on incoherent undersampling. Associated fundamental period estimation techniques along with properties of incoherent undersampling, are used to isolate the effects of periodic and periodic crosstalk jitter. Mathematical analysis and hardware experiments using commercial off-the-shelf components are performed to prove the viability of the proposed method.

Design and validation of millimeter-wave (MMW) devices is a significant challenge due to the design difficulties in meeting GHz performance constraints and the cost and complexity of test instrumentation needed to validate the circuits. In this paper a 1-V dual-core 24GHz PLL design is presented and it is shown how relatively low cost test instruments utilizing incoherent undersampling can be used to verify the noise performance of a PLL. The 24GHz PLL is implemented to provide more frequency margin and reliability for a 60GHz super-heterodyne transceiver. The incoherent undersampling method is proposed to test different performances of the PLL. Measurement results applying a sampling frequency below 1 GHz are shown for frequency reconstruction and jitter separation.

Acquisition of periodic waveforms is an integral part of characterizing high speed system performance. Various techniques are used to reduce the equipment cost, dominated by the cost of the digitizer. Incoherent under-sampling provides an attractive solution for signal acquisition. However, due to the aliasing present in under-sampled signal and the windowing effects, high resolution spectral estimation is difficult. This is especially true when under-sampling is combined with techniques such as bandwidth interleaving to extend the bandwidth of the test setup beyond the track and hold bandwidth. In this paper we propose a high resolution spectral estimation technique and propose a new setup that combines incoherent under-sampling with the bandwidth interleaving without requiring a synchronization with the signal clock. This enables waveform acquisition with bandwidth greater than the sampling track-and-hold bandwidth.

Acquisition of wide bandwidth signals is a significant problem in manufacturing test due to the cost of test equipment driven by the use of high-speed sample and hold circuitry and difficulty in data-clock synchronization. We propose to combine frequency interleaved down conversion (to overcome the bandwidth limitations of sample and hold circuitry) with incoherent undersampling (to overcome data-clock synchronization and ADC speed issues) to design a low cost instrumentation for high speed signal capture. A novel signal reconstruction algorithm is developed along with a method for calibrating the effects of unknown delays in data acquisition hardware due to mismatch in signal path lengths on the reconstructed signal. Simulation results and preliminary hardware validation prove the feasibility of the proposed technique.

High speed signal acquisition and characterization contributes a significant amount to the total test cost of the finished product in modern high speed systems. Incoherent under-sampling allows robust and low cost signal acquisition without requiring a prior accurate knowledge of signal period. In this paper we propose a frequency estimation and signal reconstruction technique for incoherently sub-sampled periodic waveforms that is based on a time domain cost function. The method reduces the per iteration cost by a factor of log N compared to frequency domain cost functions. The proposed method estimates the period of a test signal with much fewer samples without degradation of accuracy.

An active interference cancellation system is presented in BiCMOS 8HP capable of eliminating undesired signals resulting from an on-chip clock whose fundamental and/or harmonics couple into a receiver path. The cancellation system is capable of eliminating undesired clock fundamentals from 6 – 10 GHz and its harmonics up to 30 GHz. By modeling the coupling channel, the system recovers receiver sensitivity and is independent of the aggressing clock rate and amplitude fluctuations. A variable phase rotator, comb generator, and an amplitude modulator are used to achieve the cancellation. The use of a comb generator in a cancellation system is novel and enables harmonic cancellation. Over 25 dB of cancellation for an aggressing clock and its harmonics have been achieved. A series-to-parallel bus that communicates with all system sub-blocks provides a healing aspect to the system. The total power consumption of the canceller system is 71 mW.

Closed loop based quadrature generation systems depend highly on the accuracy of the phase detector. However the phase detector accuracy is susceptible to device mismatch. We present an implementation of a phase detector in SiGe BiCMOS technology and also a simple scheme for auto-zeroing of phase detector for reducing the effects of the device mismatch in phase detector and error amplifier(EA). This scheme does not require any reference signal and hence can be easily implemented at minimal overhead. Significant improvement in performance is observed for device mismatch.

This paper presents a 10-Gb/s coherent detection system incorporating feed-forward equalizers (FFEs) and an optical duobinary modulation scheme in order to increase the transmission distance limited by chromatic dispersion in standard single-mode fibers up to 400-km without signal regeneration and optical dispersion compensation. The FFE structure is based on a finite impulse response (FIR) filter with 9 taps and 100-ps tap spacing. The FFE employs capacitor-degenerated differential pairs for the delay block implementation in order to meet the system bandwidth requirement. The coherent system also incorporates a squarer for phase-diversity detection. Both the FFE and squaring circuits are fabricated in 0.18-mu m CMOS technology.

An eye-opening monitor (EOM) capable of providing qualitative two-dimensional (2D) map of the eye opening of a 10 Gbps signal is designed. The EOM is designed in 0.18 um CMOS process. The 2D map of the eye opening is obtained by scanning the eye opening with a phase-offset clock to obtain the different best-fit mask sizes. In the present design the clock is provided from an external source. The design operates with a 1.8 V supply and consumes 95 mA of current.

In this paper, two 9-taps FFE structures using different delay cell approaches are implemented and analyzed. The first FFE uses passive delay cells based on an artificial transmission line implemented using an inductor-capacitor (LC) ladder, and the second FFE uses active delay cells implemented with differential pairs incorporating an active inductive peaking technique.

In this paper, a comparative study of two different structures for the Feed Forward Equalizer (FFE) is presented to emphasize the effect of structural differences on the performance of the passive delay line based FFEs with large number of taps. Both FFEs are designed for compensation of Inter Symbol Interference (ISI) in multi-Gb/s data link. The two test structures use the same building blocks but differ in the implementation. Both of them have nine taps with passive delay cells and are designed in 0.18 mum CMOS technology.