IEEE Workshop on Microelectronics and Electron Devices : [proceedings]

In this paper, n-MOSFET and p-MOSFET are stressed using Fowler-Nordheim (F-N) tunneling and substrate hot carrier injection (HCI) to induce trapped charges. The inversion mobility is extracted and deconvoluted into surface roughness, phonon, and Coulomb mobilities. Using cryogenic measurement at 4.2K, the effect of phonon scattering is removed, allowing an accurate deconvolution of surface roughness and Coulomb mobilities. It is found that besides the Coulomb mobility being degraded after stress, the effective surface roughness mobility is also degraded.

The increasing adoption of System-in-Package (SiP) devices in critical applications has raised concerns about security vulnerabilities in advanced packaging. The complexity of heterogeneous integration (HI) and 3D architectures exposes critical communication pathways, making them prime targets for adversaries. Traditional inspection methods struggle to identify and expose asset pathways within a package located in deeply embedded structures. In this work, we employ high-resolution X-ray microscopy (XRM) as a non-destructive approach to examine interposer layers, particularly between graphics processing unit (GPU) and high-bandwidth memory (HBM). After identifying regions of interest based on this preliminary scan, we use microwave-induced plasma (MIP) etching to selectively expose interconnects while preserving structural integrity. Focused ion beam (FIB) and scanning electron microscopy (SEM) was used to further enable precise delayering and detailed analysis of interconnect vulnerabilities. This integrated workflow demonstrates how nano-probing attacks in SiP devices can potentially compromise data confidentiality. Our findings highlight the need for robust security measures in advanced packaging architectures.

This study explores the properties of spike timing dependent plasticity (STDP) in spiking neural networks (SNNs) with electrochemical field-effect transistor (ECFET) synaptic devices. STDP is a fundamental unsupervised learning mechanism in neuromorphic computing systems. Electrochemical FETs demonstrate tunable conductance through ionic drift-diffusion processes, offering biologically inspired computation. STDP behavior is demonstrated in ECFETs by analyzing the relationship between input spike timing and frequency, and subsequent modulation of the conductance between ECFET source and drain. Using advanced models that capture the dynamics of real devices, synaptic weight adjustments similar to biological neural plasticity are observed. Impacts of various device parameters on conductance tuning, weight stability are investigated. The findings reveal that ECFETs are an outstanding candidate for synapses in bioloigcally-inspired neuromorphic SNNs.

Constrained Random Verification (CRV) is the de facto standard in ASIC design flow. Parametrized tests are simulated to exercise different execution paths of a Design Under Tests (DUT). These tests are simulated multiple times to generate different test scenarios, by leveraging constrained random stimulus generation. In this work, we propose a methodology utilizing Conditional Tabular Generative Adversarial Network (CTGAN) methodology, conditioned by Upper Confidence Bound (UCB) acquisition function as a reward. The combination of CTGAN and UCB allows the selection of the most relevant test parameters to efficiently navigate the test space and generate new tests. Our methodology, evaluated in live industrial projects, is able to generate new tests, and achieve higher coverage with respect to the baseline generated from the test suite manually created by experienced DV engineers, resulting in an overall coverage improvement of 2.3%.

The increasing reliance on Printed Circuit Boards (PCBs) in critical applications such as defense, aerospace, and secure communications has heightened concerns regarding reverse engineering and counterfeiting threats. Conventional security measures, including cryptographic techniques and physical barriers, face limitations against sophisticated adversarial attacks. This paper explores the potential of integrating reconfigurable Microelectromechanical Systems (MEMS) with PCBs to enhance security. MEMS-based solutions introduce dynamic modifications to PCB characteristics, making reverse engineering more challenging while enabling tamper detection mechanisms. Various adversarial threats to PCB security are examined, alongside the vulnerabilities in the PCB supply chain. This research highlights the urgent need for advanced PCB security mechanisms through case studies of military hardware compromises. This work proposes MEMS-based reconfigurable solutions as a transformative approach to safeguarding PCBs against emerging threats.

Next-generation RF arrays will have the ability to generate data at tremendous rates. In this talk we will discuss how this data deluge can be managed using dimensionality reduction at the array. We will start by giving an overview of past approaches of dimensionality reduction, including classical beamforming and compressed sensing, and the trade-offs inherent in adaptivity and performance. We then discuss how array snapshots of broadband signals can be (provably) embedded in a low dimensional subspace without loss of array gain. One consequence of this model is a new approach to broadband beamforming, which is both computationally efficient and outperforms classical methods while being highly flexible regarding array geometry and signal bandwidth. A second consequence is a new technique for dimensionality reduction that is built directly into the analog-to-digital conversion and can dramatically reduce the hardware requirements for broadband beamforming. Finally, we will discuss how these dimensionality reduction techniques can be adapted to changing environmental conditions. To do this, we adapt ideas from two areas of active research in machine learning, online PCA algorithms and manifold optimization, to automatically adjust which features are extracted as the scene evolves.

Artificial intelligence (AI) has become the linchpin in a growing number of products, services, and research programs which are aimed at automating and enhancing the human decision-making process. There is no doubt that AI will play a central role in the future of healthcare, transportation, manufacturing, and defense, among others. However, the rapidly growing size, weight, and power (SWaP) cost of AI algorithms limit their deployment on devices with practical computing and energy constraints (satellites, wearables, wireless sensors). In this talk, I will discuss our lab's efforts to bridge this gap by closely emulating the structure and function of biological brains, with the ultimate goal of enabling AI in the most SWaP-constrained environments. This research takes a holistic approach, examining the entire AI stack, from devices and circuits to algorithms and applications. At the lowest level, I will present our research on memristor-based circuits for implementing weighted communication pathways in artificial neural networks (ANNs) and spiking neural networks (SNNs). Memristors reduce the power and latency associated with running ANNs/SNNs on traditional computer architectures by directly emulating both the memory and computation of biological synapses. In addition, memristor plasticity enables on-chip learning and allows ANNs/SNNs to function in the presence of hardware defects and process variations. Moving up the design hierarchy, the talk will highlight ideas for biologically inspired energy management in neuromorphic systems and efficient ANN/SNN topologies. Finally, the talk will provide an overview of our research related to the trustworthiness and potential security vulnerabilities of AI hardware with ties to human perception and psychology.

Engineering materials microstructure has been a critical step in developing novel materials with desired properties. Specifically in the field of electronic devices microstructure engineering is pivotal. It influences properties like conductivity, carrier mobility, and band structure in semiconductors, thin film electronics, and photovoltaics. Tailoring microstructures enhances efficiency and functionality, underpinning advancements in semiconductor technology, renewable energy, and emerging electronic applications. Traditionally, forward-based models, comprising experimental and high-fidelity approaches, have been employed in the engineering of specific microstructures. These models often rely on trial-and-error methodologies to achieve desired structural configurations. In this presentation, we introduce a novel fused data deep learning framework facilitating materials microstructure engineering through inverse design. Using a case study focused on high-entropy permanent magnets, we underscore the significance of microstructure engineering. Furthermore, we validate the model's efficacy. specifically, for FeCrCo-based permanent magnets.

The current state-of-the-art chip design process is incredibly difficult and filled with challenges across the various phases from early-stage architectural planning all the way to post-silicon characterization and production. This talk explores some of these challenges with an emphasis on I/O design and signal integrity. A few interesting problems related to the design and manufacturing of chips will be presented including applications of numerical optimization and machine learning techniques.

This presentation will expound the challenges involved in the generation of digital twins (DT) as the central tools for supporting innovation and providing informed decision support for the optimization of in-service performance of complex physical machines, devices, and components, alongside prognostics for their sustainment and life extension. A DT is comprised of a set of virtual information constructs, designed to provide an accurate in-silico representation of a physical object or system, with continual bidirectional information flow tracking the internal state, and in-service functional response of the physical twin (PT). This presentation will describe the foundational AI/ML (artificial intelligence/machine learning) concepts and frameworks needed to formulate and continuously update the DT of the selected PT. The central challenge comes from the need to establish reliable models for predicting the functional response of the PT, which is expected to exhibit highly complex, stochastic, nonlinear behavior, with functional transience conditioned on varied use conditions or service operations of the PT. This task demands a rigorous statistical treatment (i.e., uncertainty reduction, quantification and propagation through a network of human-interpretable models) and fusion of insights extracted from inherently incomplete (i.e., limited information gathered with the available sensors), uncertain, and disparate (due to diverse sources of data gathered at different times and fidelities, such as physical experiments, numerical simulations, and domain expertise) data used in calibrating both the initial model of the PT as well as its continuous update. This presentation will illustrate with examples how a suitably designed Bayesian framework combined with emergent AI/ML toolsets can uniquely address this challenge. Specifically, we will demonstrate the important roles of (i) emergent AI/ML toolsets for Bayesian inference (e.g., multi-output Gaussian process regression, generative models), (ii) high-throughput strategies for designing and employing non-standard experiments, and (iii) a SaaS platform for enabling highly efficient collaboration and knowledge sharing between distributed teams/participants in realizing the goals described above.

High-bandwidth memory (HBM) is a crucial component in most state-of-the art graphics processing units (GPUs) used for training and deploying large language models (LLMs). Although HBM has been around for nearly a decade, the recent rise in generative AI applications have driven unprecedented demand for advanced GPUs and the HBM they contain. This talk will provide an overview of HBM technology, the problems HBM solve, and some challenges and opportunities on the horizon.

This paper explores the potential of using DNA nanostructure to pattern molybdenum disulfide (MoS 2 ) for potential applications in nanoelectronics. We developed a gas phase synthesis of MoS 2 with minimal out-of-plane growth and low defect density. We used density functional theory (DFT) calculation to examine the bandgap modulation of MoS 2 due to counterion diffusion from DNA, highlighting the electron transfer mechanism during lithium intercalation. Lastly, we demonstrate deposition of DNA triangles and nanotubes on various MoS 2 surfaces. Contrary to previous results, we found that these DNA nanostructures maintained their structural stability. These findings collectively contribute valuable insights into using DNA nanotechnology to advance 2D electronics.

In this paper, the trend and variability of minimal size 65nm NMOS and PMOS transistors are measured and analyzed from 292K to 9.5K (for PMOS) and 4.2K (for NMOS). The changes and variability of the on-state current, threshold voltage, linear resistance, output resistance, and transconductance, which are important for analog applications, are extracted and analyzed. Empirical quadratic equations are developed to model the trend which can be used as handy tools for estimation. A simple methodology for rapidly calibrating the 4.2K BSIM model for the on-state currents of 65nm transistors is also proposed and demonstrated.

The semiconductor industry is facing an unprecedented headcount growth rate due to the stimulus of the US Chips and Science Act and continued growth in the demand for semiconductor products. A significant talent shortage looms on the horizon so close partnerships between industry, colleges and universities, and government entities are partnering together to increase the talent pipeline and refresh curricula, and experiential learning opportunities. Semiconductors are the "moonshot" of the next decade and we all have the opportunity to enable its success.

Deep Neural Networks (DNNs) have demonstrated revolutionary capabilities in AI, such as machine vision, natural language processing, and content generation. However, the growing energy usage due to the excessive amount of data communication between compute and memory units highlights the need to address the "Von Neumann bottleneck." In-memory computing can achieve high throughput and energy efficiency by computing multiply-accumulate (MAC) operations using Ohm's law and Kirchhoff's current law on arrays of resistive memory devices. In recent years, Analog non-volatile memory (NVM)-based accelerators with energy-efficient, weight-stationary MAC operations in analog NVM memory-array "Tiles" have been demonstrated in hardware using Phase Change Memory (PCM) devices integrated in the backend of 14-nm CMOS. Competitive end-to-end DNN accuracies can be obtained with the help of hardware-aware training, accurate weight programming, and sufficiently linear MAC operations in the analog domain. In this talk, I will share how such 14-nm PCM demonstrations build the foundation for an analog in-memory computing accelerator and discuss the co-optimization of memory devices, specialized circuits, DNN algorithms, and architecture. A highly heterogeneous and programmable accelerator architecture that takes advantage of a dense and efficient circuit switched. The 2D mesh will be presented. This flexible architecture can accelerate Transformer, Long-Short-TermMemory (LSTM), and Convolution Neural Networks (CNNs) while keeping data communication local and massively parallel.

Selective neuromodulation of peripheral nerves is an emerging treatment for neurological diseases that are resistant to traditional drug therapy. A truly low-cost and effective method of creating a custom cuff has not been accessible to researchers to prototype new methodologies and therapies in acute studies. Furthermore, deeply implanted bioelectronic devices that selectively record and stimulate peripheral nerves have the potential to revolutionize healthcare by delivering on-demand, personalized therapy. A key barrier to this goal is the lack of a miniaturized, robust, and an energy-efficient wireless link capable of transmitting data from multiple sensing channels. Here we present an inexpensive highly repeatable method to create multi-contact nerve cuffs, as well as a wireless galvanic impulse with energy-efficient, high data rate link that uses two planar electrodes on the outside of the nerve cuff to transmit data to a wearable receiver on the skin's surface at rates greater than 1Mbps.

Global digital data generation surpasses 120 ZB per year, so the demand for innovative data storage solutions is imperative. DNA-based memory is an appealing solution due to its exceptional data density, stability, and energy efficiency but it lacks a robust and scalable readout scheme. To work toward this challenge, we propose a novel DNA memory approach where DNA is used as a self-assembled, structural material to store data in three dimensions with nanometer precision and readout optically in parallel rather than through sequencing. Here, we present an imaging system that localizes fluorescently-tagged DNA in 3D through a combination of fluorescent lifetime and super-resolution microscopy. The system is comprised of a custom 16x16 single-photon avalanche diode (SPAD) array developed in a 180nm CMOS process with multiplexed photon processing for frame rates up to 80MHz. For photon timestamping, we designed a tapped delay line time-to-digital converter (TDC) with 18 ps resolution and a linearity of -0.4/+0.2 LSB. We implemented 16 parallel TDC channels on the Xilinx Zynq 7000 SoC for high-throughput lifetime readout. Next, we will integrate our imager into a microscope to image DNA storage nodes.

The project harnesses neuromorphic computing through spiking neural networks (SNNs) to enhance power grid security against disruptions. It involves using real-time digital simulation tools (such as RTDS or OPAL-RT) for analyzing power behavior in real time. This generates grid simulation data, which is then converted into neuromorphic-compatible formats through encoding. The goal is to utilize neuromorphic SNNs to identify correlations, detect anomalies, and respond to disruptions. This will result in a resilient and adaptive system capable of detecting and responding to grid anomalies with reduced power consumption, ensuring robust grid operation

This paper studies the flip-chip bonding of silicon carbide (SiC) chips onto an alumina ceramic substrate for applications at up to 600°C high temperatures. A daisy chain interconnect is formed by bonding SiC dummy chips with sputtered Ti/TaSi 2 /Pt thin film conductor pads to alumina substrate with screen-printed gold conductor pads using gold stud bumps either placed on the SiC or alumina. The package is subjected to a thermal aging process in the air at 600°C for up to eight days. Die shear tests show that the average shear force per bump is 13.3 gram force (gf) for the package with bumps formed on the SiC chip and 17.8 gf for the package with bumps formed on the alumina substrate. No significant dependence of die shear force on thermal aging days is observed. The daisy chain interconnect formed with 36 bumps in the flip-chip package is measured, when continuous, to be about 20 Ω. The resistance decreases slightly and steadily with the thermal aging days.